參數(shù)資料
型號(hào): PSD953212JIT
廠商: 意法半導(dǎo)體
英文描述: High Speed CMOS Logic Quad 2-Input NAND Gates 14-SOIC -55 to 125
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 29/110頁
文件大?。?/td> 1737K
代理商: PSD953212JIT
29/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (V
STBY
, PC2). If you have an
external battery connected to the PSD, the con-
tents of the SRAM are retained in the event of a
power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (VBATON, PC4) is High
with the supply voltage falls below the battery volt-
age and the battery on Voltage Stand-by (V
STBY
,
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (V
STBY
,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Configu-
ration.
相關(guān)PDF資料
PDF描述
PSD953212JT High Speed CMOS Logic Quad 2-Input NAND Gates 14-SOIC -55 to 125
PSD953212MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9332V15JT High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125
PSD9332V15MT High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125
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