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參數(shù)資料
| 型號： | PUMA77S4000A-35 |
| 英文描述： | 10NS, 100 PQFP, COM TEMP(EPLD) |
| 中文描述： | X32號的SRAM模塊 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 339K |
| 代理商： | PUMA77S4000A-35 |
PUMA2/67/77S4000/A-020/025/35
Issue 4.3 : December 1999
6
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP) of a low CS and a low WE.
(2) t
WR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=V
IL)
(6) D
OUT is in the same phase as written data of this write cycle.
(7) D
OUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) t
WHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.2 Timing Waveform (5)
CS1~4
tWR(2)
tCW (4)
(6)
t AW
tWC
A0~A16
t
WP(1)
DW
tDH
WE1~4
D0~31out
D0~31in
WHZ(3,9)
t AS(3)
t OW
tOH
(7)
(8)
High-Z
WE above refers to WE1~4 on the PUMA 2S4000, 67S4000A AND 77S4000A.
Low V
CC Data Retention Timing Waveform
t R
tCDR
4.5V
2.2V
4.5V
2.2V
0V
DATA RETENTION MODE
Vcc
CS1~4
V DR
CS1~4 > Vcc-0.2V
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