參數(shù)資料
型號: R5F6411FNFN
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 12/84頁
文件大?。?/td> 1206K
代理商: R5F6411FNFN
117
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Table 16-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
Table 16-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and
frequency correct, PWM mode.
Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 16-5. Modes of
operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and
three types of pulse width modulation (PWM) modes. See (Section 16.9 “Modes of Operation” on page 108).
Table 16-3. Compare Output Mode, Fast PWM(1)
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 14 or 15: Toggle OC1A on compare match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on compare match, set OC1A/OC1B at
BOTTOM (non-inverting mode)
1
Set OC1A/OC1B on compare match, clear OC1A/OC1B at
BOTTOM (inverting mode)
Note:
1.
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the com-
pare match is ignored, but the set or clear is done at BOTTOM. See
Table 16-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 9 or 11: Toggle OC1A on compare match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on compare match when up-counting. Set
OC1A/OC1B on compare match when downcounting.
1
Set OC1A/OC1B on compare match when up-counting. Clear
OC1A/OC1B on compare match when downcounting.
Note:
1.
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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R5F6411FNLG#U0 功能描述:MCU 256+8KB FLASH 100-TFLGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:M16C/R32C/100/111 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標(biāo)準(zhǔn)包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI,I²C,IEBus,IrDA,SIO,UART/USART 外圍設(shè)備:DMA,POR,PWM,WDT 輸入/輸出數(shù):121 程序存儲器容量:384KB(384K x 8) 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b,D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產(chǎn)品目錄頁面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87