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參數(shù)資料
| 型號： | RM7000A-350TI |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Released |
| 中文描述： | RM7000A⑩微處理器與片上二級高速緩存的數(shù)據(jù)資料發(fā)布 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 52K |
| 代理商： | RM7000A-350TI |
RM7000A
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
PMC- 2010739(R2)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2001
FEATURES
Dual-Issue symmetric superscalar
microprocessor
400MHz max CPU frequency
Capable of issuing two instructions
per clock cycle
Integrated primary and secondary
caches
16KB Instruction, 16KB Data, and
256KB on-chip secondary
All are 4-way set associative with
32-byte line size
Per-line locking in primary and
secondary caches
Fast Packet Cache increases
system efficiency in networking
applications
Integrated external cache controller
Allows up to 8Mbyte of external
cache for applications with large
data sets
High-performance system interface
1000 Mbyte per-second peak
throughput
125 MHz max. freq., multiplexed
address/data bus (SysAD)
Supports two outstanding reads with
out-of-order return
High-performance floating-point unit
800 MFLOPS maximum
IEEE754 compliant single and
double precision floating-point
operations
64-bit MIPS instruction set architecture
Data PREFETCH instruction allows
the processor to overlap cache miss
latency and instruction execution
Single-cycle floating-point multiply-
add
Integrated memory management unit
Fully associative TLB
64/48 dual entries map 128/96
pages
Variable page size
Embedded application enhancements
Fourteen fully prioritized vectored
interrupts-10 external, 2 internal, 2
software
Specialized DSP integer Multiply-
Accumulate instructions
(MAD/MADU), and three-operand
Multiply instruction (MUL)
I and D Test/Break-point (Watch)
registers for emulation and debug
Performance counter for system
and software tuning and debug
PACKAGING
Fully Static 0.18μ CMOS design
with dynamic power down logic
304 pin TBGA package, 31x31 mm
DEVELOPMENT TOOLS
Operating Systems:
Linux by MontaVista and Red Hat
VxWorks by Wind River Systems
Nucleus by Accelerated Technology
Neutrino by QNX Software Systems
Compiler Suites
Algorithmics
Green Hills Software
BLOCK DIAGRAM
64-bit Integer Unit
Dual-Issue Superscalar
64-bit FP Unit
Double/Single IEEE754
Integer Multiplier
D-Cache
16KB, 4-way, lockable
I-Cache
16KB, 4-way, lockable
System Control
PC Unit
MMU
Fully Assoc., 48 or 64 Entry
Bus Interface Unit
Instr. Dispatch
SysA /D Bus
System Cache (L2)
256KB, 4-way, lockable
Int Ctlr
NMI, INT9 – INT0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM7000A-400T | RM7000A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Released |
| RM7000B | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000C | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000 | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-200S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM7000A-400T | 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A400TC001 | 制造商:QED 功能描述:* |
| RM7000A-R2 | 制造商:Black Box Corporation 功能描述:4-POST OPEN RACK 42U 80.6HX 20.6"W X 29"D |
| RM7000A-R3 | 制造商:Black Box Corporation 功能描述:4 POST OPEN RACK, 42U 80.6HX 20.6"W X 29"D |
| RM7000B | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
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