參數(shù)資料
型號(hào)： SC87C51AGF40
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： CMOS single-chip 8-bit microcontrollers
中文描述： 8-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁數(shù)： 16/30頁
文件大?。?/td> 411K
代理商： SC87C51AGF40
Philips Semiconductors
Product specification
80C31/80C51/87C51
CMOS single-chip 8-bit microcontrollers
1996 Aug 16
16
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C, V
CC
= 5V
±
10%, V
SS
= 0V
1, 2, 3
24MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
1/t
CLCL
1
Oscillator frequency
Speed versions : P (24MHz)
: Y (33MHz)
VARIABLE CLOCK
4
MIN
3.5
33MHz CLOCK
MIN
MAX
MAX
33
MAX
UNIT
3.5
24
3.5
33
MHz
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrial Characteristics”, page 15.
1
ALE pulse width
43
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
21
ns
1
Address valid to ALE low
17
5
ns
1
Address hold after ALE low
17
ns
1
ALE low to valid instruction in
102
4t
CLCL
–65
55
ns
1
ALE low to PSEN low
17
t
CLCL
–25
3t
CLCL
–45
5
ns
1
PSEN pulse width
80
45
ns
1
PSEN low to valid instruction in
65
3t
CLCL
–60
30
ns
1
Input instruction hold after PSEN
0
0
0
ns
1
Input instruction float after PSEN
17
t
CLCL
–25
5t
CLCL
10
5
ns
1
Address to valid instruction in
128
70
ns
1
PSEN low to address float
10
10
ns
2, 3
RD pulse width
150
6t
CLCL
–100
6t
CLCL
–100
82
ns
2, 3
WR pulse width
150
82
ns
2, 3
RD low to valid data in
118
5t
CLCL
–90
60
ns
2, 3
Data hold after RD
0
0
0
ns
2, 3
Data float after RD
55
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
32
ns
2, 3
ALE low to valid data in
183
90
ns
2, 3
Address to valid data in
210
105
ns
2, 3
ALE low to RD or WR low
75
175
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
t
CLCL
–25
7t
CLCL
–130
40
140
ns
2, 3
Address valid to WR low or RD low
92
45
ns
2, 3
Data valid to WR transition
12
0
ns
2, 3
Data hold after WR
17
5
ns
3
Data valid to WR high
162
80
ns
2, 3
RD low to address float
0
0
0
ns
2, 3
RD or WR high to ALE high
17
67
t
CLCL
–25
t
CLCL
+25
5
55
ns
5
High time
17
17
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
5
ns
5
Low time
17
17
ns
5
Rise time
5
ns
5
Fall time
5
5
ns
4
Serial port clock cycle time
505
12t
CLCL
10t
CLCL
–133
2t
CLCL
–80
0
360
ns
4
Output data setup to clock rising edge
283
167
ns
4
Output data hold after clock rising edge
3
ns
4
Input data hold after clock rising edge
0
0
ns
4
Clock rising edge to input data valid
283
10t
CLCL
–133
167
ns
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