參數(shù)資料
型號(hào): EP3SL340F1760C3N
廠商: Altera
文件頁數(shù): 11/16頁
文件大小: 0K
描述: IC STRATIX III L 340K 1760-FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Stratix® III
LAB/CLB數(shù): 13500
邏輯元件/單元數(shù): 337500
RAM 位總計(jì): 18822144
輸入/輸出數(shù): 1120
電源電壓: 0.86 V ~ 1.15 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
1–4
Chapter 1: Stratix III Device Family Overview
Features Summary
Table 1–2 lists the Stratix III FPGA package options and I/O pin counts.
All Stratix III devices support vertical migration within the same package (for
example, you can migrate between the EP3SL50 and EP3SL70 devices in the 780-pin
FineLine BGA package). Vertical migration allows you to migrate to devices whose
dedicated pins, configuration pins, and power pins are the same for a given package
across device densities.
To ensure that a board layout supports migratable densities within one package
offering, enable the applicable vertical migration path within the Quartus II
software. On the Assignments menu, point to Device and click Migration Devices.
You can migrate from the L family to the E family without increasing the number of
LEs available. This minimizes the cost of vertical migration.
Table 1–3 lists the Stratix III FineLine BGA (FBGA) package sizes.
Table 1–2. Package Options and I/O Pin Counts (Note 1)
Device
484-Pin
FineLine
BGA (2)
780-Pin
FineLine
BGA (2)
1152-Pin
FineLine
BGA (2)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
EP3SL50
296
488
EP3SL70
296
488
EP3SL110
488
744
EP3SL150
488
744
EP3SL200
488 (5)
744
976
EP3SL340
744 (4)
976
1,120
EP3SE50
296
488
EP3SE80
488
744
EP3SE110
488
744
EP3SE260
488 (5)
744
976
Notes to Table 1–2:
(1) The arrows indicate vertical migration.
(2) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
CLK10p,
and CLK10n) that can be used for data inputs.
(3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p,
CLK8n, CLK10p,
and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp,
PLL
_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp,
and PLL_R1_CLKn) that can be used for data inputs.
(4) The EP3SL340 FPGA is offered only in the H1152 package, but not offered in the F1152 package.
(5) The EP3SE260 and EP3SL200 FPGAs are offered only in the H780 package, but not offered in the F780 package.
Table 1–3. FineLine BGA Package Sizes
Dimension
484 Pin
780 Pin
1152 Pin
1517 Pin
1760 Pin
Pitch (mm)
1.00
Area (mm2)
529
841
1,225
1,600
1,849
Length/Width (mm
mm)
23/23
29/29
35/35
40/40
43/43
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP3SL340F1760C3NES 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA
EP3SL340F1760C4 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP3SL340F1760C4L 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP3SL340F1760C4LN 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP3SL340F1760C4N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256