參數(shù)資料
型號: SMX55161A-75HKCM
廠商: AUSTIN SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 256K X 16 VIDEO DRAM, 75 ns, CDFP64
封裝: CERAMIC, FP-64
文件頁數(shù): 50/64頁
文件大?。?/td> 1223K
代理商: SMX55161A-75HKCM
VRAM
SM55161A
Production
Austin Semiconductor, Inc.
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
54
SMJ55161A
Rev. 1.6
03/05
FIGURE 44: FULL-REGISTER TRANSFER READ-TIMING, REAL-TIME
LOAD OPERATION/LATE-LOAD OPERATION
NOTES:
A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
to from the 512 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive
transition of SC.
C. A0–A8.
D. Late load operation is defined as t
d(THRH)
< 0 ns.
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