參數(shù)資料
型號： SMX55161A-80HKCI
廠商： AUSTIN SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 256K X 16 VIDEO DRAM, 80 ns, CDFP64
封裝： CERAMIC, FP-64
文件頁數(shù)： 21/64頁
文件大?。?/td> 1223K
代理商： SMX55161A-80HKCI
VRAM
SM55161A
Production
Austin Semiconductor, Inc.
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
28
SMJ55161A
Rev. 1.6
03/05
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)1
MIN
MAX
MIN
MAX
MIN
MAX
Hold time, DSF after RAS\ low
th(SFR)
10
ns
Hold time, column address valid after RAS\ low
5
th(RLCA)
30
33
35
ns
Hold time, data valid after CASx\ low
th(CLD)
12
15
ns
Hold time, data valid after RAS\ low
5
th(RLD)
30
35
ns
Hold time, data valid after WE\ low
th(WLD)
12
15
ns
Hold time, read, WE\ high after CASx\ high
6
th(CHrd)
00
0
ns
Hold time, read, WE\ high after RAS\ high
6
th(RHrd)
00
0
ns
Hold time, write, WE\ low after CASx\low
th(CLW)
12
15
ns
Hold time, write, WE\ low after RAS\ low
5
th(RLW)
30
35
ns
Hold time, TRG\ high after WE\ low
7
th(WLG)
10
ns
Hold time, SQ valid after SC high
th(SHSQ)
22
2
ns
Hold time, DSF after RAS\ low
th(RSF)
30
35
ns
Hold time, output valid after CASx\ low
th(CLQ)
00
0
ns
td(RLCH)
70
75
80
td(RLCH)
10
13
15
Delay time, CASx\ high to RAS\ low
td(CHRL)
75
5
ns
Delay time, CASx\ low to RAS\ high
td(CLRH)
17
20
ns
Delay time, CASx\ low to WE\ low
9,10
td(CLWL)
40
48
50
ns
Delay time, RAS\ low to CASx\ low
11
td(RLCL)
15
50
20
50
20
60
ns
Delay time, column address valid to RAS\ high
td(CARH)
35
38
40
ns
Delay time, column address valid to CASx\ high
td(CACH)
35
38
40
ns
Delay time, RAS\ low to WE\ low
9
td(RLWL)
90
100
105
ns
Delay time, column address valid to WE\ low
9
td(CAWL)
55
63
65
ns
Delay time, CASx\ low to RAS\ low
8
td(CLRL)
55
5
ns
Delay time, RAS\ high to CASx\ low
8
td(RHCL)
00
0
ns
Delay time, CASx\ low to TRG\ high for DRAM read cycles
td(CLGH)
20
ns
Delay time, TRG\ high before data applied at DQ
td(GHD)
15
ns
Delay time, RAS\ low to TRG\ high
12
td(RLTH)
55
58
ns
Delay time, RAS\ low to first SC high after TRG\ high
13
td(RLSH)
70
75
ns
Delay time, RAS\ low to column address valid
td(RLCA)
12
35
15
35
15
40
ns
Delay time, TRG\ low to RAS\ high
td(GLRH)
15
20
ns
Delay time, CASx\ low to first SC high after TRG\ high
13
td(CLSH)
20
23
25
ns
Delay time, SC high to TRG\ high
12, 13
td(SCTR)
55
5
ns
Delay time, TRG\ high to RAS\ high
12
td(THRH)
-10
ns
Delay time, TRG\ high to RAS\ low
14
td(THRL)
50
55
60
ns
Delay time, TRG\ high to SC high
12
td(THSC)
15
18
20
ns
UNIT
Delay time, RAS\ low to CASx\ high
ns
-70
-75
-80
PARAMETER
SYMBOL
See Note 8
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