參數(shù)資料
型號(hào): SMX55161A-80HKCI
廠商: AUSTIN SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 256K X 16 VIDEO DRAM, 80 ns, CDFP64
封裝: CERAMIC, FP-64
文件頁(yè)數(shù): 35/64頁(yè)
文件大小: 1223K
代理商: SMX55161A-80HKCI
VRAM
SM55161A
Production
Austin Semiconductor, Inc.
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
40
SMJ55161A
Rev. 1.6
03/05
FIGURE 33: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE TIMING
TABLE 11: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE STATE TABLE
NOTES:
A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
a don’t care during this cycle.
12
3
45
Write operation (nonmasked)
L
H
Don't Care
Valid Data
Write operation with nonpersistent write-per-bit
L
Write Mask
Valid Data
Write operation with persistent write-per-bit
L
Don't Care
Valid Data
Load-write mask on either the first falling edge of CASx\
or the falling edge of WE\, whichever occurs later.
1
H
L
H
Don't Care
Write Mask
CYCLE
STATE
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