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參數(shù)資料
| 型號： | SMX55161A-80HKCI |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 256K X 16 VIDEO DRAM, 80 ns, CDFP64 |
| 封裝： | CERAMIC, FP-64 |
| 文件頁數(shù)： | 6/64頁 |
| 文件大?。?/td> | 1223K |
| 代理商： | SMX55161A-80HKCI |
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VRAM
SM55161A
Production
Austin Semiconductor, Inc.
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
14
SMJ55161A
Rev. 1.6
03/05
persistent write-per-bit
The persistent write-per-bit mode is initiated by
performing a load-write-mask-register (LMR) cycle. In the
persistent write-per-bit mode, the write-per-bit mask is
overwritten but remains valid over an arbitrary number of write
cycles until another LMR cycle is performed or power is
removed.
The LMR cycle is performed using DRAM write-cycle
timing with DSF held high on the falling edge of RAS\ and held
low on the first falling edge of CASx\. A binary code is input to
the write-mask register via the random I/O pins and latched on
either the first falling edge of CASx\ or the falling edge of WE\,
whichever occurs later. Byte write control can be applied to the
write mask during the LMR cycle. The persistent write-per-bit
mode can then be used in exactly the same way as the
nonpersistent write-per-bit mode except that the input data on
the falling edge of RAS\ is ignored. When the device is set to
the persistent write-per-bit mode, it remains in this mode and is
reset only by a CBR refresh (option-reset) cycle (see Figure 8).
FIGURE 8: Example of a Persistent Write-Per-Bit Operation
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