參數(shù)資料
型號(hào)： SNJ54BCT8244AFKR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 總線收發(fā)器
英文描述： BCT/FBT SERIES, DUAL 4-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, CQCC28
封裝： CERAMIC, LCC-28
文件頁(yè)數(shù)： 4/29頁(yè)
文件大?。?/td> 618K
代理商： SNJ54BCT8244AFKR
SN54BCT8244A, SN74BCT8244A
SCAN TEST DEVICES
WITH OCTAL BUFFERS
SCBS042E FEBRUARY 1990 REVISED JULY 1996
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
boundary-control register opcode description
The BCR opcodes are decoded from BCR bits 10, as shown in Table 3. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and show the associated PSA and PRPG algorithms.
Table 3. Boundary-Control Register Opcodes
BINARY CODE
BIT 1
→ BIT 0
MSB
→ LSB
DESCRIPTION
00
Sample inputs/toggle outputs (TOPSIP)
01
Pseudo-random pattern generation / 16-bit mode (PRPG)
10
Parallel-signature analysis/16-bit mode (PSA)
11
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
It should be noted, in general, that while the control input BSCs (bits 1716) are not included in the sample,
toggle, PSA, or PRPG algorithms, the output-enable BSCs (bits 1716 of the BSR) do control the drive state
(active or high impedance) of the selected device output terminals.
sample inputs / toggle outputs (TOPSIP)
Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each
rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs
of the normal on-chip logic. Data in the shift register elements of the output BSCs is toggled on each rising edge
of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK.
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK
and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK.
This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip
logic. Figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are
generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value
of all zeroes will not produce additional patterns.
=
1A1
1Y1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
Figure 5. 16-Bit PRPG Configuration
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