SPNS110E – AUGUST 2005 – REVISED MAY 2008 ................." />
參數(shù)資料
型號: TMS470R1A384PZQ
廠商: Texas Instruments
文件頁數(shù): 10/62頁
文件大小: 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: TMS470
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 48MHz
連通性: CAN,C2Slb,I²C,SCI,SPI
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 384KB(384K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 管件
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
Peripheral Selects and Base Addresses
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
Flash Program and Erase
The A384 device flash contains three 128K-byte memory arrays (or banks), for a total of 384K-bytes of flash, and
consists of 18 sectors. These 18 sectors are sized as follows:
SECTOR
MEMORY ARRAYS
SEGMENT
LOW ADDRESS
HIGH ADDRESS
NO.
(OR BANKS)
0
8K Bytes
0x0000_0000
0x0000_1FFF
1
8K Bytes
0x0000_2000
0x0000_3FFF
2
16K Bytes
0x0000_4000
0x0000_7FFF
3
16K Bytes
0x0000_8000
0x0000_BFFF
4
16K Bytes
0x0000_C000
0x0000_FFFF
BANK0
(128K Bytes)
5
16K Bytes
0x0001_0000
0x0001_3FFF
6
16K Bytes
0x0001_4000
0x0001_7FFF
7
16K Bytes
0x0001_8000
0x0001_BFFF
8
8K Bytes
0x0001_C000
0x0001_DFFF
9
8K bytes
0x0001_E000
0x0001_FFFF
0
32K Bytes
0x0002_0000
0x0002_7FFF
1
32K Bytes
0x0002_8000
0x0002_FFFF
BANK1
(128K Bytes)
2
32K Bytes
0x0003_0000
0x0003_7FFF
3
32K Bytes
0x0003_8000
0x0003_FFFF
0
32K Bytes
0x0004_0000
0x0004_7FFF
1
32K Bytes
0x0004_8000
0x0004_FFFF
BANK2
(128K Bytes)
2
32K Bytes
0x0005_0000
0x0005_7FFF
3
32K Bytes
0x0005_8000
0x0005_FFFF
The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.
NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution cannot occur from any sector within a bank that is being programmed or erased.
NOTE:
When the OTP sector is enabled, the rest of the flash memory is disabled. The OTP
memory can only be read or programmed from code executed out of RAM.
For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
HET RAM
The A384 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
The A384 device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These
peripheral selects are fixed and transparent to the user because they are part of the decoding scheme used by
the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 4.
18
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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