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參數(shù)資料
| 型號： | TSC2300IPAGRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 73/83頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | TSC2300IPAGRG4 |
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TSC2300
SLAS372 — NOVEMBER 2002
Digital-Effects Filter Control (continued)
BASS
DESCRIPTION
0
The digital-effects filter is off (default).
1
The digital-effects filter is on.
Bit 0 DEEMP
De-emphasis control. This bit turns ON/OFF the de-emphasis function.
Table 50. De-emphasis Control
DEEMP
DESCRIPTION
0
De-emphasis is off (default).
1
De-emphasis is on.
GPIO CONTROL REGISTER (Page 02, Address 06h)
The GPIO control register controls the GPIO pins of the TSC2300. The direction of each GPIO pin can be set
independently. For GPIOs configured as output pins, the data to be driven is written to this register. For GPIO’s
configured as inputs, the input data can be read from this register. This register also contains a bit, SDAVB which
mirrors the state of the DAVB output line.
The GPIO Control Register is formatted as follows:
BIT 15
BIT
BIT 13
BIT 12
BIT 11
BIT
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
14
10
LSB
RESV
IO5
IO 4
IO 3
IO 2
IO 1
IO 0
RESV
GPIO5
GPIO4
GPIO3
GPIO2
GPIO
1
0
Bits 15,14 RESERVED
These bits are reserved and should be written to 0. If read, they will read back as 0.
Bits [13:8] IO5- IO0
GPIO Directional Control. These 6 bits control the direction of the TSC2300’s six GPIO pins. When one of these bits is
set to one, the corresponding GPIO pin is configured as an output. When one of these bits is set to zero, the
corresponding GPIO pin is configured as an input. The default setting of these bits is zero (all inputs).
Bits 7,6 RESERVED
These bits are reserved, and should be written to 0. If read, they read back as 0.
Bits [5:0] GPIO5- GPIO0
GPIO Data. These bits control the data on the GPIO pins. When a GPIO pin is configured as an output, the data
written to one of these bits is driven on the corresponding GPIO pin. When a GPIO pin is configured as an input, the
data input on the GPIO pin is returned to the corresponding register bit, and can be read by the host processor.
DAC BASS-BOOST FILTER COEFFICIENT REGISTERS (Page 02, Addresses 07h-1Ah)
The DAC bass-boost coefficient registers implement the transfer function described . The coefficients are represented
by 16-bit 2s complement integers with values ranging from -32768 to +32767.
The DAC bass-boost coefficient registers are formatted as follows:
BIT 15
BIT
BIT 13
BIT 12
BIT 11
BIT
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
14
10
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 51. DAC Bass-Boost Coefficient Registers
75
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