
VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
53-
8AH
8CH
8EH
90H
92H
94H
96H
98H
9AH
9CH
9EH
A0-
A1H
port 5 VLAN ID
port 6 VLAN ID
port 7 VLAN ID
port 8 VLAN ID
port 9 VLAN ID
port 10 VLAN ID
port 11 VLAN ID
port 12 VLAN ID
port 13 VLAN ID
port 14 VLAN ID
port 15 VLAN ID
Server Port Mask
PORT5_VID [5:0]
PORT6_VID [5:0]
PORT7_VID [5:0]
PORT8_VID [5:0]
PORT9_VID [5:0]
PORT10_VID [5:0]
PORT11_VID [5:0]
PORT12_VID [5:0]
PORT13_VID [5:0]
PORT14_VID [5:0]
PORT15_VID [5:0]
SRV_PM
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The SRV_PM is used only when VLAN is enabled. As the VLAN
feature is enabled (i.e. all port VID’s are valid (non-zero)), the
behavior is described for the following scenarios:
A broadcast or lookup-miss packet will be forwarded to the ports of
same VLAN ID. If CPU_FWD_CFG[0]=1, the broadcast packet will
also be forwarded to CPU port.
A unicast packet destined to different VLAN will be forwarded to
CPU port if VLAN_FWD_CFG[0]=1.
A unicast packet destined to another port in the same VLAN will be
forwarded in a unicast manner.
The SRV_PM should be set for the Server ports that respond to carry
cross VLAN packets. It is recommended that all packets from the
Server stations have not any embedded VID. Only the cross VLAN
packets through the Server ports (the corresponding SRV_PM bits
are on) within different VLAN domain must carry VID.
In the source-MAC learning procedure, for packets with tagged
VID, the corresponding forwarding table entry will have NOT the
tagging bit on to make the outgoing packets destined to it with VID
tagged. All valid forwarding table entries should have non-zero
VID.
VLAN related forwarding configuration
[15:0]
A2H
This register bit is used to enable those packets destined to a
different VLAN also to be forwarded to the CPU port.
This scenario happens when the following conditions hold
simultaneously:
The destination MAC address is found in forwarding table (lookup
hit), and this entry is not static. Note that if the entry is static, its
priority is highest and the destination ports are fully determined by
the port mask field in the entry so that forwarding to CPU is not
necessary.
The source VID differs from the destination VID.
VLAN_FWD_
CFG
[0]
0
R/W
4.6 Registers of PHY Control Module
* Base Address: 1800H