參數(shù)資料
型號: W9864G6GB-6I
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA60
封裝: 6.40 X 10.10 MM, 0.65 MM PITCH, ROHS COMPLIANT, VFBGA-60
文件頁數(shù): 23/44頁
文件大?。?/td> 0K
代理商: W9864G6GB-6I
W9864G6GB
Publication Release Date: Aug. 13, 2007
- 3 -
Revision A05
1.
GENERAL DESCRIPTION
W9864G6GB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words
× 4 banks × 16 bits. Using pipelined architecture and 0.11m process technology,
W9864G6GB delivers a data bandwidth of up to 166M words per second. For different application,
W9864G6GB is sorted into the following speed grades: -6I, -7 and -7I. The -6I parts can run up to
166MHz/CL3.The -7 and -7I parts can run up to 143MHz/CL3. (The -6I and -7I grade parts which is
guaranteed to support -40°C ~ 85°C.)
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance.
2.
FEATURES
3.3V± 0.3V for -6I grade power supply
2.7V3.6V for -7/-7I grade power supply
1,048,576 words
× 4 banks × 16 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Burst read, single write operation
Byte data controlled by LDQM, UDQM
Power Down Mode
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Package: VFBGA 60 balls pitch=0.65mm
W9864G6GB is using Pb free with RoHS compliant
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