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參數(shù)資料
| 型號： | W9864G6GB-6I |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA60 |
| 封裝： | 6.40 X 10.10 MM, 0.65 MM PITCH, ROHS COMPLIANT, VFBGA-60 |
| 文件頁數(shù)： | 40/44頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W9864G6GB-6I |
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W9864G6GB
Publication Release Date: Aug. 13, 2007
- 5 -
Revision A05
5.
PIN DESCRIPTION
BALL LOCATION
PIN NAME
FUNCTION
DESCRIPTION
M1,M2,N1,N2,N6
,N7,P1,P2,P6,P7,
R6,
A0
A11
Address
Multiplexed pins for row and column address. Row
address: A0
A11. Column address: A0A7. A10 is
sampled during a precharge command to determine
if all banks are to be precharged or bank selected
by BS0, BS1.
M6,M7
BS0, BS1
Bank Select
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
A2,A6,B1,B7,C1,
C7,D1,D2,D6,D7,
E1,E7,F1,F7,G1,
G7
DQ0
DQ15
Data
Input/ Output
Multiplexed pins for data output and input.
L7
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
K6
RAS
Row Address
Strobe
Command input. When sampled at the rising edge
of the clock RAS , CAS and WE define the
operation to be executed.
K7
CAS
Column
Address
Strobe
Referred to RAS
J7
WE
Write Enable
Referred to RAS
J2,J6
UDQM
LDQM
Input/output
mask
The output buffer is placed at Hi-Z (with latency of
2) when DQM is sampled high in read cycle.
In
write cycle, sampling DQM high will block the write
operation with zero latency.
K2
CLK
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
L1
CKE
Clock Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
A7,H6,R7
VDD
Power (+3.3V)
Power for input buffers and logic circuit inside
DRAM.
A1,H2,R1
VSS
Ground
Ground for input buffers and logic circuit inside
DRAM.
B6,C2,E6,F2
VDDQ
Power (+3.3V)
for I/O buffer
Separated power from VDD, to improve DQ noise
immunity.
B2,C6,E2,F6
VSSQ
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
G2,G6,H1,H7,J1,
K1,L2,L6
NC
No Connection No connection
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| W9864G6GH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 16 BITS SDRAM |
| W9864G6GH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 16 BITS SDRAM |
| W9864G6GH-6 | 制造商:Winbond Electronics Corp 功能描述:4*16BIT SDRAM |
| W9864G6GH-6I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 16 BITS SDRAM |
| W9864G6GH-7 | 制造商:Winbond Electronics Corp 功能描述:64M 3.3V SDRAM 4M X 16 |
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