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參數(shù)資料
| 型號： | XC3S5000-5FGG900C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 124/272頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 5M 900-FBGA |
| 產(chǎn)品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 27 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 8320 |
| 邏輯元件/單元數(shù)： | 74880 |
| RAM 位總計： | 1916928 |
| 輸入/輸出數(shù)： | 633 |
| 門數(shù)： | 5000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 900-BBGA |
| 供應商設備封裝： | 900-FBGA |
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Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
21
Supply Voltages for the IOBs
Three different supplies power the IOBs:
The VCCO supplies, one for each of the FPGA’s I/O banks, power the output drivers, except when using the GTL and
GTLP signal standards. The voltage on the VCCO pins determines the voltage swing of the output signal.
VCCINT is the main power supply for the FPGA’s internal logic.
The VCCAUX is an auxiliary source of power, primarily to optimize the performance of various FPGA functions such as
I/O switching.
The I/Os During Power-On, Configuration, and User Mode
With no power applied to the FPGA, all I/Os are in a high-impedance state. The VCCINT (1.2V), VCCAUX (2.5V), and VCCO
supplies may be applied in any order. Before power-on can finish, VCCINT, VCCO Bank 4, and VCCAUX must have reached
their respective minimum recommended operating levels (see Table 29, page 59). At this time, all I/O drivers also will be in
a high-impedance state. VCCO Bank 4, VCCINT, and VCCAUX serve as inputs to the internal Power-On Reset circuit (POR).
A Low level applied to the HSWAP_EN input enables pull-up resistors on User I/Os from power-on throughout configuration.
A High level on HSWAP_EN disables the pull-up resistors, allowing the I/Os to float. If the HSWAP_EN pin is floating, then
an internal pull-up resistor pulls HSWAP_EN High. As soon as power is applied, the FPGA begins initializing its
configuration memory. At the same time, the FPGA internally asserts the Global Set-Reset (GSR), which asynchronously
resets all IOB storage elements to a Low state.
Upon the completion of initialization, INIT_B goes High, sampling the M0, M1, and M2 inputs to determine the configuration
mode. At this point, the configuration data is loaded into the FPGA. The I/O drivers remain in a high-impedance state (with
or without pull-up resistors, as determined by the HSWAP_EN input) throughout configuration.
The Global Three State (GTS) net is released during Start-Up, marking the end of configuration and the beginning of design
operation in the User mode. At this point, those I/Os to which signals have been assigned go active while all unused I/Os
remain in a high-impedance state. The release of the GSR net, also part of Start-up, leaves the IOB registers in a Low state
by default, unless the loaded design reverses the polarity of their respective RS inputs.
In User mode, all internal pull-up resistors on the I/Os are disabled and HSWAP_EN becomes a “don’t care” input. If it is
desirable to have pull-up or pull-down resistors on I/Os carrying signals, the appropriate symbol—e.g., PULLUP,
PULLDOWN—must be placed at the appropriate pads in the design. The Bitstream Generator (Bitgen) option UnusedPin
available in the Xilinx development software determines whether unused I/Os collectively have pull-up resistors, pull-down
resistors, or no resistors in User mode.
CLB Overview
For more details on the CLBs, refer to the chapter entitled “Using Configurable Logic Blocks” in UG331.
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB comprises four interconnected slices, as shown in Figure 11. These slices are grouped in
pairs. Each pair is organized as a column with an independent carry chain.
The nomenclature that the FPGA Editor—part of the Xilinx development software—uses to designate slices is as follows:
The letter ‘X’ followed by a number identifies columns of slices. The ‘X’ number counts up in sequence from the left side of
the die to the right. The letter ‘Y’ followed by a number identifies the position of each slice in a pair as well as indicating the
CLB row. The ‘Y’ number counts slices starting from the bottom of the die according to the sequence: 0, 1, 0, 1 (the first CLB
row); 2, 3, 2, 3 (the second CLB row); etc. Figure 11 shows the CLB located in the lower left-hand corner of the die. Slices
X0Y0 and X0Y1 make up the column-pair on the left where as slices X1Y0 and X1Y1 make up the column-pair on the right.
For each CLB, the term “l(fā)eft-hand” (or SLICEM) indicates the pair of slices labeled with an even ‘X’ number, such as X0, and
the term “right-hand” (or SLICEL) designates the pair of slices with an odd ‘X’ number, e.g., X1.
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| XC3S500E-4CP132C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 500K GATES 10476 CELLS 572MHZ 90NM 1.2V 132C - Trays |
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| XC3S500E-4CPG132C | 功能描述:IC SPARTAN-3E FPGA 500K 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3E 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC3S500E-4CPG132I | 功能描述:IC FPGA SPARTAN-3E 500K 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3E 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
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