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參數資料
| 型號： | μPD42S65405 |
| 廠商： | NEC Corp. |
| 英文描述： | 16,777,216 Words by 4 Bits CMOS Dynamic RAMs(64M 動態(tài)RAM) |
| 中文描述： | 16,777,216詞由4位的CMOS動態(tài)存儲器（RAM的6400動態(tài)） |
| 文件頁數： | 6/36頁 |
| 文件大?。?/td> | 256K |
| 代理商： | ΜPD42S65405 |
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μ
PD4264405, 42S65405, 4265405
6
Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.
1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle’s falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose t
RAC
is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO) , read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
Hyper Page Mode (EDO) Read Cycle
t
HPC
t
OEA
t
OEZ
t
AA
t
CAC
Hi - Z
Hi - Z
Row
Col.A
Col.B
Col.C
t
OEA
t
OLZ
RAS
V
IH
–
V
IL
–
CAS
V
IH
–
V
IL
–
Address
V
IH
–
V
IL
–
V
IH
–
V
IL
–
OE
V
IH
–
V
IL
–
I/O
V
OH
–
V
OL
–
Data out A
Data out B
Data out C
Data out C
t
OEZ
t
AA
t
CAC
t
OEZ
t
OEP
t
OEP
t
OCH
t
CHO
t
CHO
WE
t
RAC
t
AA
t
CAC
t
CLZ
t
CLZ
t
WPZ
t
DHC
t
OFC
t
OFR
t
WEZ
t
OCH
t
RRH
t
RCH
相關PDF資料 |
PDF描述 |
|---|---|
| μPD4264405 | 16,777,216 Words by 4 Bits CMOS Dynamic RAMs(64M 動態(tài)RAM) |
| μPD4265405 | 16,777,216 Words by 4 Bits CMOS Dynamic RAMs(64M 動態(tài)RAM) |
| μPD42S65805 | 8,388,608 Words by 8 Bits CMOS dynamic RAMs(64M 動態(tài)RAM) |
| μPD4264805 | 8,388,608 Words by 8 Bits CMOS dynamic RAMs(64M 動態(tài)RAM) |
| μPD4265805 | 8,388,608 Words by 8 Bits CMOS dynamic RAMs(64M 動態(tài)RAM) |
相關代理商/技術參數 |
參數描述 |
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| PD430 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| PD4306 | 制造商:POWEREX 制造商全稱:Powerex Power Semiconductors 功能描述:POW-R-BLOK Dual SCR Isolated Module (600 Amperes / Up to 2400 Volts) |
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| PD430807 | 功能描述:SCR MOD ISO DUAL 800V 700A RoHS:是 類別:半導體模塊 >> SCR 系列:- 其它有關文件:SCR Module Selection Guide 標準包裝:10 系列:- 結構:串聯 - SCR/二極管 SCR 數目，二極管:1 SCR，1 個二極管 電壓 - 斷路:1600V 電流 - 柵極觸發(fā)電流 (Igt)（最大）:150mA 電流 - 導通狀態(tài) (It (AV))（最大）:95A 電流 - 導通狀態(tài) (It (RMS))（最大）:210A 電流 - 非重復電涌，50、60Hz (Itsm):1785A，1870A 電流 - 維持(Ih):250mA 安裝類型:底座安裝 封裝/外殼:ADD-A-PAK（3 + 2） 包裝:散裝 其它名稱:*IRKL92/16AIRKL92/16IRKL92/16-ND |
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