參數(shù)資料
型號: μPD4564163
廠商: NEC Corp.
英文描述: 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
中文描述: 6400位同步DRAM(6400同步動態(tài)RAM)的
文件頁數(shù): 33/84頁
文件大?。?/td> 697K
代理商: ΜPD4564163
33
μ
PD4564441, 4564841, 4564163 for Rev. E
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Write
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D4
D5
(t
RAS
must be satisfied)
Write
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D5
T8
D4
(t
RAS
must be satisfied)
相關(guān)PDF資料
PDF描述
μPD4564441 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
μPD4564841 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
μPD4564323 64M-bit Synchronous DRAM(64M 同步動態(tài)RAM)
μPD45D128164 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
μPD45D128442 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
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