參數(shù)資料
型號: μPD4811650
廠商: NEC Corp.
英文描述: 16M Synchronous Graphics Memory (SGRAM)(16M同步圖形存儲器)
中文描述: 1,600同步圖形存儲器(SGRAM)(1,600同步圖形存儲器)
文件頁數(shù): 25/96頁
文件大?。?/td> 1517K
代理商: ΜPD4811650
25
μ
PD4811650 for Rev. E
Preliminary Data Sheet
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A10 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
/CAS latency
Wrap type
Burst length
: A10 through A7
: A6 through A4
: A3
: A2 through A0
Following mode register programming, no command can be asserted before at least 2 CLK (t
RSC
) have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. The table in
16.2
Relationship between Frequency and Latency
shows the relationship of /CAS latency to the clock period and the
speed grade of the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page (256 columns).
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The
μ
PD4811650 supports “Sequential
mode” and “Interleave mode”.
The table in
7.1 Burst Length and Sequence
shows the addressing sequence for each burst length.
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