參數(shù)資料
型號: μPD70F3003
廠商: NEC Corp.
英文描述: 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器)
中文描述: 16/32位單片機微控制器(16/32位單片微控制器)
文件頁數(shù): 120/141頁
文件大?。?/td> 374K
代理商: ΜPD70F3003
CHAPTER 8 PIPELINE
108
(2) TST1
[Pipeline]
– : Idle inserted for wait
[Description]
The pipeline consists of 8 stages, IF, ID, EX1, MEM, EX2, EX3, MEM, and WB. However, no
operation is performed in the second MEM and WB stages, because there is no second memory
access nor data write to registers.
In the case of this instruction, the memory access is read modify write, and the EX and MEM
stage require 3 and 2 clocks, respectively.
8.2.10 Special instructions
(1) LDSR, STSR
[Pipeline]
[Description]
The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed
in the MEM stage, because memory is not accessed. Also, if the STSR instruction using the
EIPC and FEPC system registers is placed immediately after the LDSR instruction setting these
registers, data wait time occurs. For details, see Section
8.3 Pipeline Disorder
.
(2) NOP
[Pipeline]
[Description]
The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed
in the EX, MEM and WB stages, because no operation and no memory access is executed,
and no data is written to registers.
(3) EI, DI
[Pipeline]
[Description]
The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed
in the MEM and WB stages, because memory is not accessed and data is not written to
registers.
TST1 instruction
Next instruction
Next to next instruction
IF
ID
IF
EX1
MEM
ID
IF
EX3
MEM
EX
ID
WB
MEM
EX
WB
MEM
WB
EX2
1
2
3
4
5
6
7
8
9
10
IF
ID
IF
EX
ID
MEM
EX
WB
MEM
WB
LDSR, STSR instruction
Next instruction
1
2
3
4
5
6
IF
ID
IF
EX
ID
EX
MEM
WB
NOP instruction
Next instruction
MEM
WB
1
2
3
4
5
6
IF
ID
IF
EX
ID
MEM
EX
WB
MEM
WB
EI, DI instruction
Next instruction
1
2
3
4
5
6
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