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參數(shù)資料
| 型號： | μPD72012 |
| 廠商： | NEC Corp. |
| 英文描述： | Hub Controller For USB(集線器控制器) |
| 中文描述： | 集線器控制器的USB（集線器控制器） |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 342K |
| 代理商： | ΜPD72012 |
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Preliminary Data Sheet S13918EJ2V0DS00
9
μ
PD72012
(3/3)
Pin No.
Note 1
Pin Name
I/O
Signal Name
Function
31(37)
CLKSEL
I
CLK SELECT
Pin for selecting whether to use 48-MHz oscillator or 4-MHz crystal
oscillator (refer to
Table 1-1
).
32(38)
DV
DD
(Buffer)
-
DVDD
(Buffer)
3.3-V power supply. Since this pin is the power supply for the internal
outer buffer, connect it to a stabilized independent power supply.
(39)
DV
DD
-
DVDD
3.3-V power supply. Since this pin is the power supply for the internal
logic, connect it to a stabilized independent power supply.
This pin is used together with pin No. 32 internally in the shrink DIP
product.
33(40)
PP1
O
PORTPOWER#1
Low active open drain output pin that controls downstream port #1
power supply.
Input the output of this pin to the power control element of an external
circuit.
If not using this pin, leave it unconnected.
Note 2
34(41)
PP2
O
PORTPOWER#2
Low active open drain output pin that controls downstream port #2
power supply.
circuit.
If not using this pin, leave it unconnected.
Note 2
35(42)
PP3
O
PORTPOWER#3
Low active open drain output pin that controls downstream port #3
power supply.
Input the output of this pin to the power control element of an external
circuit.
If not using this pin, leave it unconnected.
Note 2
36(43)
PP4
O
PORTPOWER#4
Low active open drain output pin that controls downstream port #4
power supply.
Input the output of this pin to the power control element of an external
circuit.
If not using this pin, leave it unconnected.
Note 2
37(44)
PP5
O
PORTPOWER#5
Low active open drain output pin that controls downstream port #5
power supply.
Input the output of this pin to the power control element of an external
circuit.
If not using this pin, leave it unconnected.
Note 2
38(1)
DV
DD
-
DVDD
(TS0)
Test pin of
μ
PD72012 (corresponds to TS0 pin in
μ
PD72011).
Connect to digital V
DD
.
39(2)
DGND
-
DGND
Connect to digital GND. Since this pin is the GND for the internal logic,
connect it to a stabilized independent GND.
40(3)
PSSEL
I
Power SW
Pin that selects switching between bus power and self-power (refer to
Table 1-2
).
To make high level, pull up to 3.3 V.
41(4)
PVSEL
I
Port Value
Pin that selects switching between number (4 or 5) of downstream
ports (refer to
Table 1-2
).
To make high level, pull up to 3.3 V.
42(5)
DGND
-
DGND
(TS2)
Test pin of
μ
PD72012 (corresponds to TS2 pin in
μ
PD72011).
Connect to digital GND.
Notes 1.
QFP pin numbers are shown in ( ).
For details, refer to
Table 1-4
of
1.2 Tables by Pin Function
.
2.
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