
11
CHAPTER 1 GENERAL
Figure 1-4. Block Diagram of
μ
PD78014Y Subseries
Remarks 1.
The internal ROM and RAM capacities differ depending on the model.
2.
( ):
μ
PD78P014Y
TO0/P30
TI0/INTP0/P00
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
ANI0/P10-
ANI7/P17
AV
DD
AV
SS
AV
REF
INTP0/P00-
INTP3/P03
BUZ/P36
CLOCK OUTPUT
CONTROL
PCL/P35
BUZZER OUTPUT
INTERRUPT
CONTROL
A/D
CONVERTER
SERIAL
INTERFACE 1
SERIAL
INTERFACE 0
WATCH TIMER
WATCHDOG
TIMER
8-bit TIMER/
EVENT COUNTER 2
8-bit TIMER/
EVENT COUNTER 1
16-bit TIMER/
EVENT COUNTER
78K/0
CPU CORE
ROM
RAM
V
DD
V
SS
IC
(V
PP
)
SYSTEM
CONTROL
EXTERNAL
ACCESS
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
P00
P01-P03
P04
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
AD0/P40-
AD7/P47
A8/P50-
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
X2
XT1/P04
XT2