320
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018FY SUBSERIES)
ACKT
Makes SDA0 (SDA1) low immediately after execution of setting instruction (ACKT = 1) until falling edge of
next SCL.
Used to generate ACK signal by software when 8-clock wait is selected.
This bit is cleared to 0 when transfer of serial interface is started or when CSIE0 = 0.
R/W
ACKE
Acknowledge signal automatic output control
0
Disables automatic output of acknowledge signal (output by ACKT is enabled).
Used for transmission, or reception with 8-clock wait selected.
Enables automatic output of acknowledge signal.
Outputs acknowledge signal in synchronization with falling edge of 9th clock of SCL (automatically outputs
when ACKE = 1).
This bit is not automatically cleared to 0 after acknowledge signal has been output.
Used for reception with 9-clock wait selected.
1
R/W
R
ACKD
Acknowledge detection
Clearing conditions (ACKD = 0)
When transfer start instruction is executed
When CSIE0 = 0
When RESET is input
Setting condition (ACKD = 1)
When acknowledge signal is detected at rising edge
of clock of SCL after completion of transfer
BSYE
Controls N-ch open-drain output for transmission in I C bus mode
0
Enables output (transmission)
R/W
Note 3
1
Disables output (reception)
Note 1
Note 4
Note 2
Figure 16-4. Format of Serial Bus Interface Control Register (2/2)
Notes 1.
Set this bit before starting transfer.
2.
Output the acknowledge signal during reception by using ACKT when 8-clock wait is selected.
3.
The wait mode can be released when transfer by the serial interface has been started when an
address signal has been received. However, the BSYE flag is not cleared to 0.
4.
Be sure to set BSYE to 1 when using the wake-up function.
Remark
CSIE0: Bit 7 of the serial operation mode register 0 (CSIM0)