183
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-5. Format of 16-Bit Timer Mode Control Register
Cautions 1. Before changing the clear mode and output timing of TO0, stop the timer operation (set
TMC01 through TMC03 to 0, 0, 0).
2. The valid edge of the TI0/INTP0 pin is set by the external interrupt mode register (INTM0). The
frequency of the sampling clock is selected by the sampling clock select register (SCS).
3. When using the PWM mode, set the PWM mode and then set data to CR00.
4. When a mode in which the 16-bit timer is cleared and started on coincidence between TM0
and CR00 is selected, the OVF0 flag is set to 1 when the value of TM0 changes from FFFFH
to 0000H with FFFFH set to CR00.
Remark
TO0
TI0
TM0 : 16-bit timer register
CR00 : 16-bit compare register
: Output pin of 16-bit timer/event counter
: Input pin of 16-bit timer/event counter
6
5
4
3
2
1
<0>
7
Symbol
TMC0
0
0
0
0
TMC03 TMC02 TMC01
OVF0
OVF0
0
1
Detects overflow in 16-bit timer register
Overflow does not occur
Overflow occurs
FF48H 00H R/W
Address On reset R/W
TMC03
Selects operation
mode or clear mode
TMC02 TMC01
0
Stops operation
(TM0 is cleared to 0)
0
0
Selects timing of
TO0 output
Not affected
Generated when
TM0 coincides with CR00
0
PWM mode (free running)
0
1
PWM pulse output
0
Free running mode
1
0
Coincidence between
TM0 and CR00
0
1
1
Coincidence between TM0
and CR00 or valid edge of TI0
1
Clear and start
at valid edge of Tl0
0
0
Coincidence between
TM0 and CR00
1
0
1
Coincidence between TM0
and CR00 or valid edge of Tl0
1
Clear and start at coincidence
between TM0 and CR00
1
0
Coincidence
between TM0 and CR00
1
1
1
Coincidence between TM0
and CR00 or valid edge of Tl0
Not generated
Generates interrupt