487
CHAPTER 24 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
PUSH
PSW
1
4
–
(SP – 1)
←
PSW, SP
←
SP – 1
rp
1
8
–
(SP – 1)
←
rp
H
, (SP – 2)
←
rp
L
,
SP
←
SP – 2
POP
PSW
1
4
–
PSW
←
(SP), SP
←
SP + 1
R
R
R
rp
1
8
–
rp
H
←
(SP + 1), rp
L
←
(SP),
SP
←
SP + 2
MOVW
SP, #word
4
–
20
SP
←
word
SP, AX
2
–
16
SP
←
AX
AX, SP
2
–
16
AX
←
SP
BR
!addr16
3
12
–
PC
←
addr16
$addr16
2
12
–
PC
←
PC + 2 + jdisp8
AX
2
16
–
PC
H
←
A, PC
L
←
X
BC
$addr16
2
12
–
PC
←
PC + 2 + jdisp8 if CY = 1
BNC
$addr16
2
12
–
PC
←
PC + 2 + jdisp8 if CY = 0
BZ
$addr16
2
12
–
PC
←
PC + 2 + jdisp8 if Z = 1
BNZ
$addr16
2
12
–
PC
←
PC + 2 + jdisp8 if Z = 0
BT
saddr.bit, $addr16
3
16
18
PC
←
PC + 3 + jdisp8 if(saddr.bit) = 1
sfr.bit, $addr16
4
–
22
PC
←
PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
3
16
–
PC
←
PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16
3
–
18
PC
←
PC + 3 + jdisp8 if PSW.bit = 1
[HL].bit, $addr16
3
20
22 + 2n PC
←
PC + 3 + jdisp8 if (HL).bit = 1
BF
saddr.bit, $addr16
4
20
22
PC
←
PC + 4 + jdisp8 if(saddr.bit) = 0
sfr.bit, $addr16
4
–
22
PC
←
PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
3
16
–
PC
←
PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16
4
–
22
PC
←
PC + 4 + jdisp8 if PSW. bit = 0
[HL].bit, $addr16
3
20
22 + 2n PC
←
PC + 3 + jdisp8 if (HL).bit = 0
Notes 1.
When the internal high-speed RAM area is accessed or when an instruction that does not access data
is executed
2.
When an area other than the internal high-speed RAM area is accessed
Remarks 1.
One clock of an instruction is equal to one CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2.
The number of clocks shown is when the program is stored in the internal ROM area.
3.
n indicates the number of wait states when the external memory extension area is read.
Mnemonic
Operand
Byte
Operation
Stack
manipulation
Instruction
Group
Unconditional
branch
Conditional
branch