130
78K/0 SERIES APPLICATION NOTE
Figure 8-3. Format of Serial Operating Mode Register 0 (Only for the
μ
PD78044F
and
μ
PD780208 Subseries) (1/2)
Notes 1.
Bit 6 (COI) is read-only.
2.
When only transmission is performed, this pin can be used as P25 (CMOS input).
3.
This pin can be used for a port function.
4.
When the wakeup function is used (WUP = 1), set bit 5 (SIC) of the interrupt timing specification
register (SINT) to 0.
Caution The operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI mode) must not be changed
while serial interface channel 0 is enabled. To change the operating mode, temporarily
stop serial operation beforehand.
Remark
x
: Don’t care
PMxx: Port mode register
Pxx
: Port output latch
*
*
CSIM0
Symbol
Address
At reset
R/W
FF60H
00H
R/W
Note 1
R/W
SI0/SB0/P25
pin function
SO0/SB1/P26
pin function
SCK0/P27
pin function
R/W
Wakeup function control
Note 4
An interrupt request signal is issued at each serial transfer in all of the modes.
When the address received after the bus release in the SBI mode (when CMDD = RELD = 1) matches the data
in the slave address register, an interrupt request signal is issued.
SCK0
(CMOS I/O)
SI0
Note 2
(input)
MSB
LSB
MSB
MSB
Operating
mode
3-wire serial
I/O mode
WUP
0
1
P27
1
1
1
1
1
PM27
0
0
0
0
0
P26
0
0
0
PM26
P25
PM25
CSIM
02
0
1
0
1
0
1
x
0
1
0
1
1
Note 3
x
0
0
0
Note 3
x
x
0
0
1
0
0
CSIM
03
CSIM
04
R/W
Input clock from the outside to pin SCK0
x
0
1
0
1
1
CSIM
00
CSIM
01
Clock selection for serial interface channel 0
2
3
4
0
1
7
6
5
CSIM
02
CSIM
03
CSIM
04
CSIM
00
CSIM
01
CSIE
0
COI
WUP
Output of the 8-bit timer register 2 (TM2)
Clock specified by bits 0 to 3 of the timer clock selection register 3 (TCL3)
First
bit
SO0
(CMOS output)
Note 3
x
Note 3
x
Note 3
x
Note 3
x
Note 3
x
Note 3
x
SBI mode
2-wire serial
I/O mode
P25
(CMOS I/O)
SB0
N-channel
open drain I/O
P25
(CMOS I/O)
SB0
N-channel
open drain I/O
SB1
N-channel
open drain I/O
P26
(CMOS I/O)
SB1
N-channel
open drain I/O
P26
(CMOS I/O)
SCK0
(CMOS I/O)
SCK0
N-channel
open drain I/O