
55
μ
PD78052, 78053, 78054, 78055, 78056, 78058
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
t
KCY9
4.5 V
≤
V
DD
≤
6.0 V
800
ns
2.7 V
≤
V
DD
< 4.5 V
1600
ns
3200
ns
SCK1 high/low-level width
t
KH9
,
t
KL9
V
DD
= 4.5 to 6.0 V
t
KCY9
/2 – 50
ns
t
KCY9
/2 – 100
ns
SI1 setup time (to SCK1
↑
)
t
SIK9
4.5 V
≤
V
DD
≤
6.0 V
100
ns
2.7 V
≤
V
DD
< 4.5 V
150
ns
300
ns
SI1 hold time (from SCK1
↑
)
t
KSI9
400
ns
SO1 output delay time from SCK1
↓
t
KSO9
C = 100 pF
Note
300
ns
STB
↑
from SCK1
↑
t
SBD
t
KCY9
/2 – 100
t
KCY9
/2 + 100
ns
Strobe signal high-level width
t
SBW
V
DD
= 2.7 to 6.0V
t
KCY9
– 30
t
KCY9
+ 30
ns
t
KCY9
– 60
t
KCY9
+ 60
ns
Busy signal setup time
(to busy signal detection timing)
t
BYS
100
ns
Busy signal hold time
(from busy signal detection timing)
t
BYH
4.5 V
≤
V
DD
≤
6.0 V
100
ns
2.7 V
≤
V
DD
< 4.5 V
150
ns
200
ns
SCK1
↓
from busy inactive
t
SPS
2t
KCY9
ns
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Note
C is the load capacitance of the SO1 output line.
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
t
KCY10
4.5 V
≤
V
DD
≤
6.0 V
800
ns
2.7 V
≤
V
DD
< 4.5 V
1600
ns
3200
ns
SCK1 high/low-level width
t
KH10
,
t
KL10
4.5 V
≤
V
DD
≤
6.0 V
400
ns
2.7 V
≤
V
DD
< 4.5 V
800
ns
1600
ns
SI1 setup time (to SCK1
↑
)
t
SIK10
100
ns
SI1 hold time (from SCK1
↑
)
t
KIS10
400
ns
SO1 output delay time from SCK1
↓
t
KSO10
C = 100 pF
Note
300
ns
SCK1 rise, fall time
t
R10
, t
F10
When using external device
expansion function
160
ns
When not using external device
expansion function
1000
ns
Note
C is the load capacitance of the SO1 output line.