5
m
PD78062, 78063, 78064
FUNCTIONAL OUTLINE
16K bytes
512 bytes
24K bytes
32K bytes
1024 bytes
40
¥
4 bits
8 bits
¥
32 registers (8 bits
¥
8 registers
¥
4 banks)
On-chip instruction execution time cycle modification function
0.4
m
s/0.8
m
s/1.6
m
s/3.2
m
s/6.4
m
s/12.8
m
s (at 5.0 MHz operation)
122
m
s (at 32.768 kHz operation)
16-bit operation
Multiplication/division (8 bits
¥
8 bits,16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, boolean operation)
BCD correction, etc.
Total
CMOS input
CMOS I/O
8-bit resolution
¥
8 channels
Segment signal output : Maximum 40
Common signal output : Maximum 4
Bias : 1/2 or 1/3 switchable
3-wire serial I/O/SBI/2-wire serial I/O mode selectable
3-wire serial I/O/UART mode selectable
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
: 57
:
0
2
: 55
: 1 channel
: 1 channel
:
:
:
:
1 channel
2 channels
1 channel
1 channel
3 (14-bit PWM output capability : 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
5.0 MHz (at main system clock 5.0 MHz operation)
32.768 kHz (at subsystem clock 32.768 kHz operation)
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0 MHz operation)
Internal : 12, external :
6
Internal : 1
1
Internal:
1, external: 1
V
DD
= 2.0 to 6.0 V
100-pin plastic QFP (Fine pitch) (14
¥
14 mm, resin thickness: 1.45 mm)
100-pin plastic QFP (14
¥
20 mm)
100-pin plastic LQFP (Fine pitch) (14
¥
14 mm, resin thickness: 1.40 mm)
ROM
High-speed RAM
LCD display RAM
m
PD78064
m
PD78063
m
PD78062
Instruction set
LCD controller/driver
Serial interface
Timer
Internal
memory
When main system clock
selected
When subsystem clock
selected
I/O ports
(including segment signal output pins)
A/D converter
Vectored
interrupt
sources
Package
Maskable
Non-maskable
Softwar
Item
Product Name
General registers
Instruction cycle
Timer output
Clock output
Buzzer output
Test input
Supply voltage