參數資料
型號： μPD78075B
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8 Bit Single Chip Microcontrollers
中文描述： 8位單片機微控制器
文件頁數： 30/76頁
文件大小： 568K
代理商： ΜPD78075B
30
μ
PD78074B, 78075B
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions
A total of 24 interrupt functions are provided, divided into the following three types.
Non-maskable
: 1
Maskable
: 22
Software
: 1
Table 6-1. List of Interrupt Sources
Interrupt
Type
Default
Priority
Interrupt Source
Internal/
External
Vector
Table
Address
Basic
Configura-
tion Type
Name
Trigger
Non-
maskable
Maskable
—
INTWDT
Overflow of watchdog timer (When the watchdog
timer mode 1 is selected)
Overflow of watchdog timer (When the interval
timer mode is selected)
Pin input edge detection
Internal
0004H
(A)
0
INTWDT
(B)
1
2
3
4
5
6
7
8
9
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTCSI0
INTCSI1
INTSER
External
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
(C)
(D)
Completion of serial interface channel 0 transfer
Completion of serial interface channel 1 transfer
Occurrence of serial interface channel 2 UART
reception error
Completion of serial interface channel 2 UART reception
Completion of serial interface channel 2 3-wire transfer
Completion of serial interface channel 2 UART
transmission
Reference interval signal from watch timer
Generation of matching signal of 16-bit timer register
and capture/compare register (CR00)
Generation of matching signal of 16-bit timer register
and capture/compare register (CR01)
Generation of matching signal of 8-bit timer/event
counter 1
Generation of matching signal of 8-bit timer/event
counter 2
Completion of A/D conversion
Generation of matching signal of 8-bit timer/event
counter 5
Generation of matching signal of 8-bit timer/event
counter 6
Internal
(B)
10
11
INTSR
INTCSI2
INTST
001AH
12
001CH
13
14
INTTM3
INTTM00
001EH
0020H
15
INTTM01
0022H
16
INTTM1
0024H
17
INTTM2
0026H
18
19
INTAD
INTTM5
0028H
002AH
20
INTTM6
002CH
Software
—
BRK
Execution of BRK instruction
—
003EH
(E)
Notes 1.
Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest order and 20 is the lowest order.
2.
Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Note 2
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