– vii –
FIGURE (2/4)
Fig. No.
Title
Page
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
8-Bit Timer Mode Control Register Setting for External Event Counter Operation.............
External Event Counter Operation Timings (with Rising Edge Specification) ....................
8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ..............
8-Bit Timer Mode Control Register Settings for PWM Output Operation ...........................
PWM Output Operation Timing (Active high setting) ..........................................................
PWM Output Operation Timings (CRn0 = 00H, active high setting)...................................
PWM Output Operation Timings (CRn0 = FFH, active high setting) ..................................
PWM Output Operation Timings (CRn0 changing, active high setting)..............................
8-Bit Timer Registers 5 and 6 Start Timing.........................................................................
External Event Counter Operation Timing ..........................................................................
Timing after Compare Register Change during Timer Count Operation ............................
93
93
94
96
97
97
98
99
100
100
101
7-1
7-2
7-3
Watchdog Timer Block Diagram .........................................................................................
Timer Clock Select Register 2 Format................................................................................
Watchdog Timer Mode Register Format.............................................................................
105
107
108
8-1
8-2
8-3
8-4
Remote Controlled Output Application Example ................................................................
Clock Output Control Circuit Block Diagram.......................................................................
Timer Clock Select Register 0 Format................................................................................
Port Mode Register 3 Format .............................................................................................
111
112
113
114
9-1
9-2
9-3
Buzzer Output Control Circuit Block Diagram ....................................................................
Timer Clock Select Register 2 Format................................................................................
Port Mode Register 3 Format .............................................................................................
115
117
118
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
A/D Converter Block Diagram ............................................................................................
A/D Converter Mode Register Format ................................................................................
A/D Converter Input Select Register Format ......................................................................
External Interrupt Mode Register 1 Format ........................................................................
A/D Converter Basic Operation ..........................................................................................
Relations between Analog Input Voltage and A/D Conversion Result................................
A/D Conversion by Hardware Start ....................................................................................
A/D Conversion by Software Start......................................................................................
Example of Method of Reducing Current Dissipation in Standby Mode.............................
Analog Input Pin Disposition ..............................................................................................
A/D Conversion End Interrupt Request Generation ...........................................................
Handling of AVDD Pin.........................................................................................................
120
123
124
125
127
128
129
130
131
132
133
11-1
11-2
11-3
11-4
11-5
11-6
Serial Interface Channel 2 Block Diagram .........................................................................
Baud Rate Generator Block Diagram .................................................................................
Serial Operating Mode Register 2 Format..........................................................................
Asynchronous Serial Interface Mode Register Format.......................................................
Asynchronous Serial Interface Status Register Format .....................................................
Baud Rate Generator Control Register Format (1/2) .........................................................
137
138
140
141
143
144