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Preliminary Product Information
42
μ
PD789216Y, 789217Y
(2) Buzzer output control register (BZC90)
Based on the count clock (fcl) selected with the count clock selection bits (TCL901 and TCL900), this register
sets a buzzer frequency and controls square wave output
BZC90 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears BZC90 to 00H.
Figure 6-13. Format of Buzzer Output Control Register
BZOE90
Buzzer port output control
Disables buzzer port output.
Enables buzzer port output.
Note
0
1
0
0
0
0
BCS902
BCS901
BCS900
BZOE90
BZC90
Symbol
Address
When reset
R/W
FF49H
00H
R/W
6
7
5
4
BCS902
BCS901
BCS900
Buzzer frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
2
1
0
fcl = f
CC
/2
2
fcl = f
CC
/2
6
fcl = f
CC
/2
7
fcl = f
XT
fcl/2
4
(62.5 kHz)
fcl/2
5
(31.3 kHz)
fcl/2
8
(3.91 kHz)
fcl/2
9
(1.95 kHz)
fcl/2
10
(977 Hz)
fcl/2
11
(488 Hz)
fcl/2
12
(244 Hz)
fcl/2
13
(122 Hz)
fcl/2
4
(3.91 kHz)
fcl/2
5
(1.95 kHz)
fcl/2
8
(244 Hz)
fcl/2
9
(122 Hz)
fcl/2
10
(61 Hz)
fcl/2
11
(30.5 Hz)
fcl/2
12
(15.3 Hz)
fcl/2
13
(7.63 Hz)
fcl/2
4
(1.95 kHz)
fcl/2
5
(977 Hz)
fcl/2
8
(122 Hz)
fcl/2
9
(61 Hz)
fcl/2
10
(30.5 Hz)
fcl/2
11
(15.3 Hz)
fcl/2
12
(7.63 Hz)
fcl/2
13
(3.81 Hz)
fcl/2
4
(2.05 kHz)
fcl/2
5
(1.02 kHz)
fcl/2
8
(128 Hz)
fcl/2
9
(64 Hz)
fcl/2
10
(32 Hz)
fcl/2
11
(16 Hz)
fcl/2
12
(8 Hz)
fcl/2
13
(4 Hz)
Note
When setting BZOE90 to 1, TOE82 must be fixed to 0. (See
Figure 6-20
.)
Cautions 1. Bits 4 to 7 must be fixed to 0.
2. If the subclock is selected as the count clock (TCL901 = 1, TCL900 = 1: see Figure 6-12), the
subclock is not synchronized when buzzer port output is enabled. In this case, the capture
function and TM90 register read function are disabled. In addition, the count value of the
TM90 register is undefined.
Remarks 1.
f
CC
: Main system clock oscillation frequency
2.
f
XT
: Subsystem clock oscillation frequency
3.
The parenthesized values apply to operation at f
CC
= 4.0 MHz or f
XT
= 32.768 kHz.