
6
Main Revisions in This Edition
Page
Description
pp. 127 to 131, 137
Change of following block diagrams of ports:
Figures 6-5
and
6-7 P20, P21, and P23 to P26 Block Diagram
,
Figure 6-6
and
6-8 P22 and P27
Block diagram
,
Figure 6-9 P30 to P37 Block Diagram
, and
Figure 6-16 P71 and P72 Block
Diagram
pp. 153
Addition of
Table 7-2 Relationships between CPU Clock and Minimum Instruction Execution
Time
pp. 226, 231
Addition of
Figures 9-10
and
9-13 Square Wave Output Operation Timing
pp. 291
Connection of Note on BSYE in
Figure 16-5 Serial Bus Interface Control Register Format
pp. 302
Addition of Caution to
16.4.3 (2) (a) Bus release signal (REL)
and
(b) Command signal (CMD)
pp. 394
Addition of
(3) MSB/LSB switching as the start bit
to
18.4.2 3-wire serial I/O mode operation
pp. 416 to 420
Change of
18.4.3 (3) (d) Busy control option
,
(e) Busy & strobe control option
, and
(f) Bit
shippage detection function
in old edition to
(4) Synchronization control
, and improvement of
explanation
pp. 454
Correction of
Figure 19-11 Receive Error Timing
pp. 461
Addition of
(3) MSB/LSB switching as the start bit
to
19.4.3 3-wire serial I/O mode
pp. 463
Addition of
19.4.4 Restrictions in UART mode
pp. 536
Addition of Note to
26.1 Memory Size Switching Register
pp. 538
26.3 Flash Memory Programming
Change of product name of flash programmer from Flashpro to Flashpro II
pp. 559
Addition of
APPENDIX A DIFFERENCES AMONG
μ
PD78054, 78058F, AND 780058 SUBSERIES
pp. 561 to 573
APPENDIX B DEVELOPMENT TOOLS
Total revision: Support of in-circuit emulators IE-78K0-NS and IE-78001-R-A
pp. 575 to 576
APPENDIX C EMBEDDED SOFTWARE
Total revision: Deletion of fuzzy inference development support system
pp. 583
Addition of
APPENDIX E REVISION HISTORY
The mark shows major revised points.