
– vii –
7-4
7-5
7-6
7-7
7-8
7-9
7-10
Timing of Interval Timer Operation ......................................................................................................... 90
Timing of External Event Counter Operation (with rising edge specified) ............................................ 92
PWM Output Operation Timing ............................................................................................................... 95
Operation Timing When CR5n Is Changed ............................................................................................ 96
16-Bit Resolution Cascade Mode............................................................................................................ 98
Start Timing of 8-Bit Counter 5n (TM5n) ................................................................................................ 99
Timing after Changing Compare Register Value during Timer Count Operation.................................. 99
8-1
8-2
8-3
8-4
Watchdog Timer Block Diagram ............................................................................................................ 102
Oscillation Stabilization Time Select Register Format ......................................................................... 103
Watchdog Timer Clock Select Register Format ................................................................................... 104
Watchdog Timer Mode Register Format ............................................................................................... 105
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
A/D Converter Block Diagram ............................................................................................................... 110
A/D Converter Mode Register Format .................................................................................................. 112
Analog Input Channel Specification Register Format .......................................................................... 113
Basic Operation of A/D Converter ......................................................................................................... 115
Relation between Input Analog Voltage and A/D Conversion Result .................................................. 116
A/D Conversion by Software Start ........................................................................................................ 117
Example of Reducing Current Consumption in Standby Mode ........................................................... 118
Processing of Analog Input Pin ............................................................................................................. 119
A/D Conversion End Interrupt Request Generation Timing ................................................................. 120
Processing of AV
DD
Pin.......................................................................................................................... 120
10-1
10-2
10-3
Serial Interface Block Diagram .............................................................................................................. 122
Format of Serial Operation Mode Register 3 ....................................................................................... 123
Timing in Three-Wire Serial I/O Mode .................................................................................................. 126
11-1
11-2
11-3
11-4
11-5
11-6
FIP Controller/Driver Block Diagram ..................................................................................................... 128
Display Mode Register 0 Format ........................................................................................................... 130
Display Mode Register 1 Format ........................................................................................................... 131
Display Mode Register Format .............................................................................................................. 132
Blanking Width of FIP Output Signal .................................................................................................... 133
Relation between Address Location of Display Data Memory and FIP Output
(with 48 FIP output pins and 16 patterns) ............................................................................................ 134
Leakage Emission Because of Short Blanking Time ........................................................................... 136
Leakage Emission Caused by C
SG
....................................................................................................... 137
Leakage Emission Caused by C
SG
....................................................................................................... 138
Total Power Dissipation P
T
(T
A
= –40 to +85 °C).................................................................................. 139
Relationship between Display Data Memory and FIP Output
with 10 Segments-11 Digits Displayed ................................................................................................. 141
11-7
11-8
11-9
11-10
11-11
LIST OF FIGURES (2/3)
Figure No.
Title
Page