參數(shù)資料
型號： μPD78P058FY
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8 Bit Single Chip Microcontrollers
中文描述： 8位單片機(jī)微控制器
文件頁數(shù)： 24/74頁
文件大?。?/td> 520K
代理商： ΜPD78P058FY
μ
PD78P058FY
24
(1)
Read mode
Read mode is set if CE = L, OE = L are set.
(2)
Output disable mode
Data output becomes high-impedance, and is in the output disable mode, if OE = H is set.
Therefore, it allows data to be read from any device by controlling the OE pin, if multiple
μ
PD78P058FYs are
connected to the data bus.
(3)
Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4)
Page data latch mode
Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode.
In this mode, 1-page 4-byte data is latched in an internal address/data latch circuit.
(5)
Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed
by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification
can be performed, if CE = L, OE = L are set.
If programming is not performed by a one-time program pulse, X (X
≤
10) write and verification operations should
be executed repeatedly.
(6)
Byte write mode
Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE =
H. Then, program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, X (X
≤
10) write and verification operations should
be executed repeatedly.
(7)
Program verify mode
Program verify mode is set if CE = L, PGM = H, OE = L are set.
In this mode, check if a write operation is performed correctly after the write.
(8)
Program inhibit mode
Program inhibit mode is used when the OE pin, V
PP
pin, and D0 to D7 pins of multiple
μ
PD78P058FYs are
connected in parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At this
time, a write is not performed to a device which has the PGM pin driven high.
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