參數(shù)資料
型號(hào)： μSAP703000-B04
廠商： NEC Corp.
英文描述： 8 Bit Single Chip Microcontrollers(8位單片微控制器)
中文描述： 8位單片機(jī)微控制器（8位單片微控制器）
文件頁(yè)數(shù)： 17/51頁(yè)
文件大?。?/td> 132K
代理商： ΜSAP703000-B04
17
CHAPTER 1 GENERAL
1.2.1 PCM-to-linear conversion block
This block converts a 64-kbps PCM code (8 bits) into a linear code (14 bits: expressed as 2’s complement).
The PCM code in the
μ
-law mode is converted by a PCM decoder conforming to Recommendation G.711.
The PCM code in the A-law mode is converted by a PCM decoder conforming to Recommendation G.711. The
resulting value is doubled and then adjusted to 14 bits.
1.2.2 ADPCM compression block
This block compresses a linear code (14 bits) to an ADPCM code (32 kbps: 4 bits, 16 kbps: 2 bits) in the following
procedure (refer to
Figure 1-4
):
(1) A predicted signal is subtracted from the input signal (linear code) to calculate a differential signal.
(2) The differential signal is coded by using an adaptive quantization unit.
For 32-kbps ADPCM, the differential signal is coded to 4 bits by using a 15 level adaptive quantization unit.
For 16-kbps ADPCM, the differential signal is coded to 2 bits by using a 4 level adaptive quantization unit.
This coded signal is an ADPCM code and is the output of the compression processing.
(3) An adaptive reverse quantization unit is used to generate a quantized differential signal from the ADPCM code.
(4) The quantized differential signal is added to the predicted signal to reproduce the input signal.
(5) An adaptive prediction unit is used to calculated the predicted value of the next input signal from the reproduced
signal and quantized differential signal.
Figure 1-4. Organization of ADPCM Compression Block
Linear code
(14 bits)
+
+
–
Differential
signal
Adaptive
quantization unit
32 kbps : 15 levels
16 kbps : 4 levels
ADPCM code
(32 kbps : 4 bits)
(16 kbps : 2 bits)
Adaptive
prediction unit
Reproduced
signal
+
+
+
Quantized
differential signal
Adaptive reverse
quantization unit
32 kbps : 15 levels
16 kbps : 4 levels
Predicted
signal
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