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參數(shù)資料
| 型號： | 01AL |
| 英文描述： | 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER |
| 中文描述： | 2:1差分至的LVPECL復(fù)用器 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 301K |
| 代理商： | 01AL |
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
8
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
APPLICATION INFORMATION
FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 1A shows an example of the differential input that
can be wired to accept single ended LVCMOS levels. The
reference voltage level V
BB generated from the device is
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 1B shows an example of the differential input that
can be wired to accept single ended LVPECL levels. The
reference voltage level V
BB generated from the device is
connected to the negative input.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
VCC(or VDD)
CLK_IN
PCLK
nPCLK
VBB
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