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參數(shù)資料
| 型號： | 100231006 |
| 英文描述： | REDUZIERVERBINDUNG ZAPF 1MM ROHR 6MM |
| 中文描述： | REDUZIERVERBINDUNG察普夫1mm的羅爾毫米 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 269K |
| 代理商： | 100231006 |
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
120
AC ELECTRICAL CHARACTERISTICS (for Plastic Leaded Chip Carrier)
10H20EV8: 0
°C ≤ Tamb ≤ +75°C, VEE = –5.2V ± 5%, VCC = VCO1 = VCO2 = GND
10020EV8: 0
°C ≤ Tamb ≤ +85°C, –4.8V ≤ VEE ≤ –4.2V, VCC = VCO1 = VCO2 = GND
LIMITS1
SYMBOL
PARAMETER
FROM
TO
0
°C
+25
°C
+75
°C/+85°C
UNIT
MIN
TYP3
MAX
2
MIN
TYP3
MAX
2
MIN
TYP3
MAX
2
Pulse Width
tCKH
Clock High
CLK +
CLK –
2.0
0.6
2.0
0.6
2.0
0.6
ns
tCKL
Clock Low
CLK –
CLK +
2.0
0.9
2.0
0.9
2.0
0.9
ns
tCKP
Clock Period
CLK +
4.0
ns
tPRH
Preset/Reset Pulse
(I, I/O)
±
(I, I/O)
±
4.5
—
4.5
—
4.5
—
ns
Setup and Hold Time
tIS
Input
(I, I/O)
±
CLK +
2.5
1.0
2.5
1.1
2.6
1.4
ns
tIH
Input
CLK +
(I, I/O)
±
0
< 0
0
< 0
0
< 0
ns
tPRS
Clock Resume after
Preset/Reset
(I, I/O)
±
CLK +
4.5
1.0
4.5
0.9
4.5
0.8
ns
Propagation Delay
tPD
Input
(I, I/O)
±
I/O
±
2.85
4.5
2.95
4.5
3.35
4.5
ns
tCKO
Clock
CLK +
I/O
±
1.65
2.2
1.7
2.2
2.0
2.3
ns
tOE
Output Enable
(I, I/O)
±
I/O
2.0
4.0
2.1
4.0
2.2
4.0
ns
tOD
Output Disable
(I, I/O)
±
I/O
2.0
4.0
2.1
4.0
2.2
4.0
ns
tPRO
Preset/Reset
(I, I/O)
±
I/O
±
2.8
4.5
3.0
4.5
3.5
4.5
ns
tPPR
Power-on Reset
VEE
I/O
—
10
—
10
—
10
ns
fMAX
212
377
212
357
204
294
MHz
NOTES:
1. Refer to AC Test Circuit and Voltage Wafeforms diagrams.
2. Maximum loading conditions: 89 fuses intact per row.
3. Typical loading conditions: 15 fuses intact per row. (All “inactive” fuses, except those necessary for correct functionality, are removed.)
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