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參數(shù)資料
| 型號： | 100336SC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Power 4-Stage Counter/Shift Register |
| 中文描述： | 100K SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO24 |
| 封裝： | 0.300 INCH, MS-013, SOIC-24 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 318K |
| 代理商： | 100336SC |
Military Version
AC Characteristics
V
EE
= 4.2V to 5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= 55C
Min
325
0.40
T
C
= +25C
Min
325
0.50
T
C
= +125
Min
325
0.40
Units
Conditions
Notes
Max
Max
Max
f
shift
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Shift Frequency
Propagation Delay
CP to Q
n
, Q
n
Propagation Delay
CP to TC (Shift)
Propagation Delay
CP to TC (Count)
Propagation Delay
MR to Q
n
, Q
n
Propagation Delay
MR to TC (Count)
Propagation Delay
MR to TC (Shift)
Propagation Delay
D
0
/CET to TC
Propagation Delay
S
n
to TC
Transition Time
20% to 80%, 80% to
20%
Setup Time
D
3
P
n
D
0
/CET
CEP
S
n
MR (Release Time)
Hold Time
D
3
P
n
D
0
/CET
CEP
S
n
Pulse Width
HIGH:
CP
MR
MHz
ns
Figures 2, 3
Figures 1, 3
(Note 11)
2.30
2.20
2.50
(Notes 8, 9, 10, 12)
1.30
3.90
1.70
3.80
1.70
4.20
ns
Figures 1, 7, 8
1.20
4.60
1.50
4.60
1.60
5.20
ns
Figures 1, 9
(Notes 8, 9, 10, 12)
0.60
2.90
0.80
2.80
0.90
3.20
ns
Figures 1, 4
(Notes 8, 9, 10, 12)
2.30
5.20
2.70
5.20
2.90
5.90
ns
Figures 1, 12
2.10
4.30
2.20
4.10
2.40
4.70
ns
Figures 1, 10, 11
(Notes 8, 9, 10, 12)
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
0.70
3.20
1.00
3.20
1.30
4.10
ns
Figures 1, 5
(Notes 8, 9, 10, 12)
1.30
4.10
1.50
4.20
1.70
4.90
ns
0.20
1.90
0.20
1.80
0.20
2.00
ns
Figures 1, 3
(Note 11)
t
s
1.40
1.70
1.80
1.80
3.30
2.60
1.40
1.70
1.80
1.80
3.30
2.60
1.40
1.70
1.80
1.80
3.30
2.60
ns
Figure 6
(Note 11)
t
h
0.90
1.00
0.70
0.60
0.00
1.60
0.90
1.00
0.70
0.60
0.00
1.60
0.90
1.00
0.70
0.60
0.00
1.60
ns
Figure 6
(Note 11)
t
pw
(H)
ns
Figures 3, 4
(Note 11)
2.00
2.00
2.00
Note 8:
F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold tempertures.
Note 9:
Screen tested 100% on each device at +25C temperature only, Subgroups A9.
Note 10:
Sample tested (Method 5005, Table I) on each manufactured lot at +25C, SubgroupsA9, and at +125C and 55C temperatures, SubgroupsA10 andA11.
Note 11:
Not tested at +25C, +125C, and 55C temperature (design characterization data).
Note 12:
The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
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