參數(shù)資料
型號(hào): 100343DM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 8-Bit D-Type Latch
中文描述: 100K SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP24
封裝: CERAMIC, DIP-24
文件頁數(shù): 4/8頁
文件大小: 155K
代理商: 100343DM
Military Version
AC Electrical Characteristics
(Continued)
V
EE
= 4.2V to 5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= 55C
Min
0.90
T
C
= +25C
Min
1.0
T
C
= +125C
Min
1.10
Units
Conditions
Notes
Max
3.40
Max
3.10
Max
3.90
t
PLH
t
PHL
t
TLH
t
THL
t
s
Propagation Delay
LE, E to Output
Transition Time
20% to 80%, 80% to 20%
Setup Time
ns
Figures 1, 2, 3
(Notes 8, 9,
10, 12)
0.40
2.50
0.40
2.40
0.40
2.70
ns
Figures 1, 3
(Note 11)
D
0
–D
7
0.60
0.60
0.60
ns
Figures 1, 4
(Note 11)
t
h
Hold Time
D
0
–D
7
1.50
1.50
1.70
ns
Figures 1, 4
(Note 11)
t
pw
(H)
Pulse Width HIGH
LE, E
2.40
2.40
2.40
ns
Figures 1, 4
(Note 11)
Note 8:
F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.
Note 9:
Screen tested 100% on each device at +25C temperature only, Subgroup A9.
Note 10:
Sample tested (Method 5005, Table I) on each manufactured lot at +25C, Subgroup A9, and at +125C and 55C temperatures, Subgroups A10 and A11.
Note 11:
Not tested at +25C, +125C, and 55C temperature (design characterization data).
Note 12:
The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Test Circuitry
Switching Waveforms
DS100298-6
Note 13:
V
CC
, V
CCA
= +2V, V
EE
= 2.5V
Note 14:
L1 and L2 = equal length 50
impedance lines
R
T
= 50
terminator internal to scope
Decoupling 0.1 μF from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
= Fixture and stray capacitance
3 pF
FIGURE 1. AC Test Circuit
DS100298-7
FIGURE 2. Propagation Delays
www.national.com
4
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