參數(shù)資料
型號(hào): 100355
廠商: Fairchild Semiconductor Corporation
英文描述: Low Power Quad Multiplexer/Latch(低功耗、四鎖存器/多路器)
中文描述: 低功耗四多路復(fù)用器/鎖存(低功耗,四鎖存器/多路器)
文件頁數(shù): 6/10頁
文件大?。?/td> 88K
代理商: 100355
www.fairchildsemi.com
6
1
Industrial Version
PLCC DC Electrical Characteristics
(Note 6)
V
EE
=
4.2V to
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
40
°
C to
+
85
°
C
Note 6:
The specified limits represent the
worst case
value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under
worst case
conditions.
PLCC AC Electrical Characteristics
V
EE
=
4.2V to
5.7V, V
CC
=
V
CCA
=
GND
Symbol
Parameter
T
C
=
40
°
C
Min
1085
1830
1095
T
C
=
0
°
C to
+
85
°
C
Min
1025
1830
1035
Units
Conditions
Max
870
1575
Max
870
1620
V
OH
V
OL
V
OHC
V
OLC
V
IH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
mV
mV
mV
V
IN
=
V
IH (Max)
or V
IL (Min)
V
IN
=
V
IH (Min)
or V
IL (Max)
Guaranteed HIGH Signal
for ALL Inputs
Loading with
50
to
2.0V
Loading with
50
to
2.0V
Output LOW Voltage
Input HIGH Voltage
1565
870
1610
870
mV
mV
1170
1165
V
IL
Input LOW Voltage
1830
1480
1830
1475
mV
Guaranteed LOW Signal
for ALL Inputs
V
IN
=
V
IL (Min)
I
IL
I
IH
Input LOW Current
0.50
0.50
μ
A
Input HIGH Current
S
0
, S
1
E
1
, E
2
D
na
D
nd
MR
Power Supply Current
300
350
220
350
μ
A
V
IN
=
V
IH (Max)
340
430
40
340
430
40
I
EE
87
87
mA
Inputs Open
Symbol
Parameter
T
C
=
40
°
C
Min
T
C
=
+
25
°
C
Min
T
C
=
+
85
°
C
Min
Units
Conditions
Max
Max
Max
t
PLH
t
PHL
Propagation Delay
D
na
D
nd
to Output
(Transparent Mode)
Figures 1, 2
0.60
1.70
0.60
1.70
0.70
1.80
ns
t
PLH
t
PHL
Propagation Delay
S
0
, S
1
to Output
(Transparent Mode)
1.00
2.40
1.00
2.40
1.20
2.50
ns
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
t
S
Propagation Delay
E
1
, E
2
to Output
Propagation Delay
0.80
1.80
0.80
1.80
0.80
1.90
ns
0.80
2.10
0.80
2.10
0.80
2.10
ns
Figures 1, 3
MR to Output
Transition Time
20% to 80%, 80% to 20%
0.40
1.90
0.60
1.30
0.60
1.30
ns
Figures 1, 2
Setup Time
D
na
D
nd
S
0
, S
1
MR (Release Time)
Hold Time
D
na
D
nd
S
0
, S
1
0.90
2.40
0.80
1.60
0.80
1.60
ns
Figure 4
1.50
1.40
1.40
Figure 3
t
H
0.40
0.30
0.10
0.30
0.10
ns
Figure 4
0.00
t
PW
(L)
t
PW
(H)
Pulse Width LOW E
1
, E
2
Pulse Width HIGH MR
2.00
2.00
2.00
2.00
2.00
2.00
ns
ns
Figure 2
Figure 3
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