參數(shù)資料
型號: 100397
廠商: Fairchild Semiconductor Corporation
英文描述: Quad Differential ECL/TTL Translating Transceiver with Latch(帶寄存器的四差分ECL/TTL電平轉換收發(fā)器)
中文描述: 四差動ECL / TTL電閉鎖翻譯收發(fā)器(帶寄存器的四差分ECL /的TTL電平轉換收發(fā)器)
文件頁數(shù): 7/13頁
文件大?。?/td> 129K
代理商: 100397
7
www.fairchildsemi.com
1
Industrial Version
(Continued)
ECL-to-TTL DC Electrical Characteristics
(Note 11)
V
EE
=
4.2V to
5.7V, GND
=
0V, T
C
=
40
°
C to
+
85
°
C, C
L
=
50 pF, V
TTL
=
+
4.5V to
+
5.5V
Symbol
Parameter
V
OH
Output HIGH Voltage
Note 11:
The specified limits represent the
worst case
value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under
worst case
conditions.
PCC TTL-to-ECL AC Electrical Characteristics
V
EE
=
4.2V to
5.7V, V
TTL
=
+
4.5V to
+
5.5V
Min
2.7
Typ
3.1
Max
Units
V
Conditions
I
OH
=
3 mA, V
TTL
=
4.75V
I
OH
=
3 mA, V
TTL
=
4.50V
I
OL
=
24 mA, V
TTL
=
4.50V
Guaranteed HIGH Signal for All Inputs
2.4
2.9
0.3
V
V
V
OL
V
IH
V
IL
V
DIFF
V
CM
I
IH
Output LOW Voltage
Input HIGH Voltage
0.5
870
1480
1170
1830
150
mV
Input LOW Voltage
Input Voltage Differential
Common Mode Voltage
mV
mV
V
Guaranteed LOW Signal for All Inputs
Required for Full Output Swing
GNDECL
2.0
GNDECL
0.5
Input HIGH Current
E
0
E
3
, E
0
E
3
OE, LE, DIR
V
IN
=
V
IH(Max)
300
35
μ
A
I
CEX
Output HIGH
Leakage Current
Bus Drainage Test
50
μ
A
V
OUT
=
V
TTL
I
ZZ
500
μ
A
V
OUT
=
5.25V
V
TTL
=
0.0V
V
IN
=
V
IL(Min)
I
IL
I
OZHT
Input LOW Current
3-STATE Current
0.50
μ
A
70
μ
A
V
OUT
=
+
2.7V
Output HIGH
3-STATE Current
Output LOW
I
OZLT
650
μ
A
V
OUT
=
+
0.5V
I
OS
I
TTL
Output Short-Circuit Current
V
TTL
Supply Current
100
225
39
27
mA
mA
mA
V
OUT
=
0.0V, V
TTL
=
+
5.5V
TTL Outputs LOW
TTL Outputs HIGH
39
mA
TTL Outputs in 3-STATE
Symbol
Parameter
T
C
=
40
°
C
Min
180
T
C
=
+
25
°
C
Min
180
T
C
=
+
85
°
C
Min
180
Units
Conditions
Max
Max
Max
f
MAX
Maximum Clock Frequency
MHz
t
PLH
t
PHL
T
n
to E
n
, E
n
(Transparent)
0.9
2.4
0.8
2.2
0.7
2.5
ns
Figures 1, 3
t
PLH
t
PHL
LE to E
n
, E
n
1.2
2.3
1.3
2.4
1.4
2.5
ns
Figures 1, 3
t
PZH
OE to E
n
, E
n
(Cutoff to HIGH)
1.9
3.8
2.5
4.5
2.5
4.6
ns
Figures 1, 3
t
PHZ
OE to E
n
, E
n
(HIGH to Cutoff)
2.5
4.7
2.3
4.0
2.5
4.5
ns
Figures 1, 3
t
PHZ
DIR to E
n
, E
n
(HIGH to Cutoff)
T
n
to LE
T
n
to LE
Transition Time
20% to 80%, 80% to 20%
1.8
3.5
2.1
3.7
2.3
4.2
ns
Figures 1, 3
t
S
t
H
t
TLH
t
THL
0.8
0.8
0.8
ns
Figures 1, 3
0.6
0.6
0.6
ns
Figures 1, 3
0.8
2.8
0.8
2.8
0.8
2.8
ns
Figures 1, 3
相關PDF資料
PDF描述
100397QCX ECL-to-TTL Translator
100397QIX ECL-to-TTL Translator
100397QI Quad Differential ECL/TTL Translating Transceiver with Latch
100397QC Quad Differential ECL/TTL Translating Transceiver with Latch
100398PC Quad Differential ECL/TTL Translating Transceiver with Latch
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