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參數(shù)資料
| 型號(hào)： | 100600400 |
| 英文描述： | T VERBINDUNG 4MM |
| 中文描述： | ? VERBINDUNG毫米 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 269K |
| 代理商： | 100600400 |
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
128
SNAP
Features
Schematic entry using DASH 4.0 or
above or OrCAD
SDT III
State Equation Entry
Boolean Equation Entry
Allows design entry in any combination of
above formats
Simulator
– Logic and fault simulation
– Timing model generation for device
timing simulation
– Synthetic logic analyzer format
Macro library for standard TTL and user
defined functions
Device independent netlist generation
JEDEC fuse map generated from netlist
SNAP (Synthesis, Netlist, Analysis and
Program) is a versatile development tool that
speeds the design and testing of PML. SNAP
combines a user-friendly environment and
powerful modules that make designing with
PML simple. The SNAP environment gives
the user the freedom to design independent
of the device architecture.
The flexibility in the variations of design entry
methodologies allows design entry in the
most appropriate terms. SNAP merges the
inputs, regardless of the type, into a high-
level netlist for simulation or compilation into
a JEDEC fuse map. The JEDEC fuse map
can then be transferred from the host
computer to the device programer.
SNAP’s simulator uses a synthetic logic
analyzer format to display and set the nodes
of the design. The SNAP simulator provides
complete timing information, setup and
hold-time checking, plus toggle and fault
grading analysis.
SNAP operates on an IBM
PC/XT, PC/AT,
PS/2, or any compatible system with DOS
2.1 or higher. A minimum of 640K bytes of
RAM is required together with a hard disk.
DESIGN SECURITY
The 10H20EV8/10020EV8 has a
programmable security fuse that controls the
access to the data programmed in the device.
By using this programmable feature,
proprietary designs implemented in the
device cannot be copied or retrieved.
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