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參數(shù)資料
| 型號： | 108847252 |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 861K |
| 代理商： | 108847252 |
Tyco Electronics Corp.
5
Data Sheet
June 2001
3.3 Vdc and 5.0 Vdc Input, 1.5 Vdc - 3.3 Vdc Output, 5A
Austin Lite Non-Isolated SMT DC - DC Power Modules:
Output Regulation (continued)
Table 2. Output Specifications
Unless otherwise noted, all specifications are defined at nominal line, full load, TAMBIENT – 25
°C
* units will start into 5000
F, 5A load at nominal line; units will start into 10,000 F with no load
Static Voltage Regulation
The ouput voltage measured at the converter output pins on the system board will be within the range shown in
Table 3, except during turn-on and turn-off. Static voltage regulation includes:
s
DC Output initial voltage
s
Input voltage range
s
3.0V – 3.6V
s
4.5V – 5.5V
s
Load regulation from 0A – 5A
Output Ripple and Noise
Output ripple and noise is defined as periodic or random deviation from the nominal voltage at the output pins while
under constant load and input line. Typical full load output ripple and noise waveforms are shown in Figures 4 – 10.
Parameter
Device
Symbol
Min
Typ
Max
Unit
Output Voltage
These specifications are under all specified
input voltage, load current, and temperature
conditions. They do not include ripple or
transient.
3.3V
2.5V
2.0V
1.8V
1.5V
VOUT
3.20
2.42
1.94
1.74
1.45
3.3
2.5
2.0
1.8
1.5
3.400
2.58
2.06
1.86
1.55
V
Output Current
*(see Figures 17 – 22 for derating)
—
IOUT
0
—
5A
Output Ripple
(See Figures 4 — 9)
3.3 VIN
5.0 VIN
VRIPPLE
—
80
100
mVpp
External Load Capacitance*
All
——
5000*
—
F
Output Current Limit Inception
All
IOUT
7A
Efficiency
VIN = Nominal, IOUT = Maximum
5.0 – 3.3
5.0 – 2.5
3.3 – 2.5
3.3 – 2.0
3.3 – 1.8
3.3 – 1.5
η
—
87
82
86
82
80
75
—
%
Switching Frequency
All
FOP
—
900
—
kHz
VOUT Dynamic Response to Transient Load
(TTRANSITION = 50
s)
Nominal Load 50% to 100% Peak Deviation
measured as a maximum percentage deviation
from nominal VO at full load
Nominal Load 50% to 100% Settling Time to
VOUT < 10% of VOUT STEADY STATE
See Figures 10 – 15
All
—
< 10
< 25
—
%
S
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