參數(shù)資料
型號(hào)： TS(X)PC603EVGU3LL
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255
封裝： CERAMIC, BGA-255
文件頁(yè)數(shù)： 28/38頁(yè)
文件大?。?/td> 632K
代理商： TS(X)PC603EVGU3LL
TSPC603E
34/38
5.6. Instruction timing
The 603e is a pipelined superscalar processor. A pipelined processor is one in which the processing of an instruction is reduced into
discrete stages. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire
resources of an execution unit. For example, after an instruction completes the decode stage, it can pass on to the next stage, while
the subsequent instruction can advance into the decode stage. This improves the throughput of the instruction flow. For example, it
may take three cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point pipeline, a series of
floating-point instructions can have a throughput of one instruction per cycle.
The instruction pipeline in the 603e has four major pipeline stages, described a follows :
D The fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next
instruction fetch. Additionally, the BPU decodes branches during the fetch stage and folds out branch instructions before the dis-
patch stage if possible.
D The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage, and determining
which of the instructions are eligible to be dispatched in the current cycle. in addition, the source operands of the instructions are
read from the appropriate register file and dispatched with the instruction to the execute pipeline stage. At the end of the dispatch
pipeline stage, the dispatched instructions and their operands are latched by the appropriate execution unit.
D During the execute pipeline stage each execution unit that has an executable instruction executes the selected instruction (per-
haps over multiple cycles), writes the instruction’s result into the appropriate rename register, and notifies the completion stage
that the instruction has finished execution. In the case of an internal exception, the execution unit reports the exception to the
completion/writeback pipeline stage and discontinues instruction execution until the exception is handled. The exception is not
signaled until that instruction is the next to be completed. Execution of most floating-point instructions is pipelined within the FPU
allowing up to three instructions to be executing in the FPU concurrently. The pipeline stages for the floating-point unit are multiply,
add, and round-convert. Execution of most load/store instructions is also pipelined. The load/store units has two pipeline stages.
The first stage is for effective address calculation and MMU translation and the second stage is for accessing the data in the cache.
D The complete/writeback pipeline stage maintains the correct architectural machine state and transfers the contents of the rename
registers to the GPRs and FPRs as instructions are retired. If the completion logic detects an instruction causing an exception,
all following instructions are cancelled, their execution results in rename registers are discarded, and instructions are fetched from
the correct instruction stream.
A superscalar processor is one that issues multiple independent instructions into multiple pipelines allowing instructions to execute in
parallel. The 603e has five independent execution units, one each for integer instructions, floating-point instructions, branch instruc-
tions, load/store instructions, and system register instructions. The IU and the FPU each have dedicated register files for maintaining
operands (GPRs and FPRs, respectively), allowing integer calculations and floating-point calculations to occur simultaneously with-
out interference.
Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction timing among various Pow-
erPC processors varies accordingly.
6. PREPARATION FOR DELIVERY
6.1. Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
6.2. Certificate of compliance
TCS offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883
and guarantying the parameters not tested at temperature extremes for the entire temperature range.
7. HANDLING
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devi-
ces have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recom-
mended :
a) Devices should be handled on benches with conductive and grounded surfaces.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50 percent if practical.
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