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參數(shù)資料
| 型號： | 1430G5LL |
| 英文描述： | NetLight 1430G5 Type SONET/SDH Long-Reach Transceivers with Clock Recovery |
| 中文描述： | 網(wǎng)絡之光公司1430G5類型的SONET / SDH長距離收發(fā)器與時鐘恢復 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 222K |
| 代理商： | 1430G5LL |
Data Sheet, Rev 1.
August 2001
Long-Reach Transceivers with Clock Recovery
NetLight 1430G5 Type SONET/SDH
2
Agere Systems Inc.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Pin Information
1-967(F).b
Figure 1. 1430G5 and 1430H5-Type Transceivers, 20-Pin Configuration, Top View
Table 1. Transceiver Pin Descriptions
Parameter
Symbol
Min
Max
Unit
Supply Voltage
VCC
03.6
V
Operating Case Temperature Range
TC
–40
85
°C
Storage Case Temperature Range
Tstg
–40
85
°C
Lead Soldering Temperature/Time
—
250/10
°C/s
Operating Wavelength Range
λ
1.1
1.6
nm
Pin
Number
Symbol
Name/Description
Logic
Family
Receiver
MS
Mounting Studs. The mounting studs are provided for transceiver mechani-
cal attachment to the circuit board. They may also provide an optional con-
nection of the transceiver to the equipment chassis ground.
NA
1
Photode-
tector Bias
Photodetector Bias. This lead supplies bias for the PIN photodetector diode.
NA
2VEER
Receiver Signal Ground.
NA
3VEER
Receiver Signal Ground.
NA
4CLK–
Received Recovered Clock Out. The rising edge occurs at the rising edge of
the received data output. The falling edge occurs in the middle of the received
data bit period.
LVPECL
5CLK+
Received Recovered Clock Out. The falling edge occurs at the rising edge
of the received data output. The rising edge occurs in the middle of the
received data bit period.
LVPECL
6VEER
Receiver Signal Ground.
NA
7VCCR
Receiver Power Supply.
NA
8SD
Signal Detect.
Normal operation: logic one output.
Fault condition: logic zero output.
LVTTL
9
RD–
Received DATA Out. No Internal terminations will be provided.
LVPECL
10
RD+
Received DATA Out. No internal terminations will be provided.
LVPECL
6 789 10
15 14 13 12 11
20-PIN MODULE - TOP VIEW
TX
RX
12 345
20 19 18 17 16
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