參數(shù)資料
型號(hào): 15CY7C109B-15VC
英文描述: 128K x 8 Static RAM(221.62 k)
中文描述: 128K的× 8靜態(tài)RAM(221.62十一)
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 221K
代理商: 15CY7C109B-15VC
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *A
Page 5 of 12
Switching Characteristics[5] Over the Operating Range (continued)
Parameter
Description
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Unit
Min.
Max.
Min.
Max.
Min.
Read Cycle
tRC
Read Cycle Time
20
25
35
ns
tAA
Address to Data Valid
20
25
35
ns
tOHA
Data Hold from Address Change
3
5
ns
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
20
25
35
ns
tDOE
OE LOW to Data Valid
8
10
15
ns
tLZOE
OE LOW to Low Z
0
ns
tHZOE
OE HIGH to High Z[6, 7]
810
15
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z
[7]
355
ns
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z
[6, 7]
810
15
ns
tPU
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
000
ns
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
20
25
35
ns
Write Cycle[8]
tWC
Write Cycle Time[9]
20
25
35
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
152025
ns
tAW
Address Set-Up to Write End
15
20
25
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
121520
ns
tSD
Data Set-Up to Write End
10
15
20
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[7]
355
ns
tHZWE
WE LOW to High Z[6, 7]
810
15
ns
Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter
Description
Conditions
Min.
Max
Unit
VDR
VCC for Data Retention
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0
V
ICCDR
Data Retention Current
150
A
tCDR
Chip Deselect to Data Retention Time
0
ns
tR
Operation Recovery Time
200
s
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