Table A-7 lists the delays in gross memory access time for several values of VDDIO
參數(shù)資料
型號(hào)： 20-101-1105
廠商： Rabbit Semiconductor
文件頁數(shù)： 93/112頁
文件大小： 0K
描述： MODULE RCM4100 RABBITCORE
標(biāo)準(zhǔn)包裝： 1
系列： RabbitCore®
模塊/板類型： MPU 核心模塊
適用于相關(guān)產(chǎn)品： RCM4100
其它名稱： 316-1121
User’s Manual
77
Table A-7 lists the delays in gross memory access time for several values of VDDIO.
The measurements are taken at the 50% points under the following conditions.
T = -40°C to 85°C, V = VDDIO ±10%
Internal clock to nonloaded CLK pin delay
≤ 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
Tadr, the clock to address delay
TCSx, the clock to memory chip select delay
TIOCSx, the clock to I/O chip select delay
TIORD, the clock to I/O read strobe delay
TIOWR, the clock to I/O write strobe delay
TBUFEN, the clock to I/O buffer enable delay
The data setup time delays are similar for both Tsetup and Thold.
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened (sometimes lengthened) by a maximum amount given in the table above. The
shortening takes place by shortening the high part of the clock. If the doubler is not
enabled, then every clock is shortened during the low part of the clock period. The maxi-
mum shortening for a pair of clocks combined is shown in the table.
Technical Note TN227, Interfacing External I/O with Rabbit Microprocessor Designs,
contains suggestions for interfacing I/O devices to the Rabbit 4000 microprocessors.
Table A-7. Preliminary Data and Clock Delays
VDDIO
(V)
Clock to Address
Output Delay
(ns)
Data Setup
Time Delay
(ns)
Worst-Case
Spectrum Spreader Delay
(ns)
30 pF
60 pF
90 pF
0.5 ns setting
no dbl / dbl
1 ns setting
no dbl / dbl
2 ns setting
no dbl / dbl
3.3
6
8
11
1
2.3 / 2.3
3 / 4.5
4.5 / 9
1.8
18
24
33
3
7 / 6.5
8 / 12
11 / 22
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