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參數(shù)資料
| 型號(hào)： | 20-668-0024 |
| 廠商： | Rabbit Semiconductor |
| 文件頁(yè)數(shù)： | 95/358頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU RABBIT4000 128-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Rabbit 4000 |
| 處理器類(lèi)型： | Rabbit 4000 8-位 |
| 速度： | 60MHz |
| 電壓： | 2.5V，2.7V，3V，3.3V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 20-668-0022 316-1078 |
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174
Rabbit 4000 Microprocessor User’s Manual
The DMA operation is controlled by memory structures called buffer descriptors. The cur-
rent buffer descriptor resides in the registers of the DMA channel, but may have been
placed there either by the processor or loaded directly by the DMA channel itself. Buffer
descriptors may be used singly, to transfer one block of data, or they may be linked together
for “scatter-gather” operation. Each DMA channel also contains an “initial address” that
points to the first buffer descriptor in memory and allows the DMA channel to rewind itself
automatically in the case of a transmit retry by the network port. Each buffer descriptor
contains a control byte, a byte count for the data, a source address, a destination address,
and an optional link address. In addition, each DMA channel retains a count of the number
of bytes remaining in the buffer to allow software to determine the amount of valid data in
a buffer that are terminated early by the source of the data.
A buffer descriptor in memory consists of either 12 or 16 consecutive bytes organized as
shown in Table 19-1. The DMA channel uses the information in the control byte to deter-
mine the length of the buffer descriptor as well as which information to fetch from the
buffer descriptor. If no link address field is present, the buffer descriptor is only 12 bytes
long. A memory address for either source or destination causes the DMA channel to fetch
three bytes from the corresponding field in the buffer descriptor. An internal I/O or exter-
nal I/O address for either source or destination causes the DMA channel to fetch two bytes
from the corresponding field in the buffer descriptor.
DMA memory addresses are always physical addresses, and are never translated by the
MMU. All DMA memory addresses use the memory control signals, wait states, and
flipped bits as selected in the Master Memory Bank Control registers. All DMA external
I/O addresses use the I/O control signals and wait states as selected in the external I/O
registers.
The first byte in the first buffer descriptor (the byte pointed to by the initial address) is
reserved for status information when transferring data from an internal serial or network
device. This automatic status transfer means that the processor does not need to service
any interrupts from a serial or network receiver except in the case of an error condition.
When transferring data to an internal HDLC serial or network transmitter, the last byte of
the last buffer will automatically be written to a special destination address to tag the data
as the last in the frame, without processor intervention. However, this function is not
available in the case where the buffer contains only one byte of data. If this case should
occur, the buffer descriptor must contain the special destination address.
All the DMA channels request interrupts at the same priority level, which is set by a field
in the DMA Master Control Register, but each DMA channel has its own interrupt vector
location. This speeds up interrupt processing for the DMA interrupts by eliminating the
need to resolve which DMA channel is actually requesting an interrupt.
DMA transfers may be programmed to occur at any priority level. If the programmed level
is greater than or equal to the current CPU operating level, DMA transfers will occur on
demand. When the CPU operating level is greater than the programmed DMA operating
level, no DMA transfers can occur. This allows interrupt services routines, or other critical
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