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參數(shù)資料
| 型號： | 2032VL |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | 2.5V的在系統(tǒng)可編程超快⑩高密度可編程邏輯器件 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 156K |
| 代理商： | 2032VL |
Specifications
ispLSI 2032VL
7
ispLSI 2032VL Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
#335
I/O Pin
(Input)
Y0,1,2
GRP
#22
GLB Reg Bypass
#28
ORP Bypass
#37
D
Q
RST
RE
OE
CK
I/O Delay
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#25, 26, 27
#43, 44
#36
Reset
Ded. In
#21
#31, 32
#38,
39
GOE 0
#42
#40, 41
0491/2032VL
Comb 4 PT Bypass #23
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
3.5ns
(0.5 + 0.6 + 2.9) + (1.7) - (0.5 + 0.6 + 1.1)
=
=
=
=
(0.5 + 0.6 + 4.1) + (1.3) - (0.5 + 0.6 + 2.9)
=
=
=
=
(0.5 + 0.6 + 4.1) + (0.3) + (1.7 + 1.8)
t
su
2.5ns
9.0ns
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
t
co
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
Table 2-0042/2032VL
Note: Calculations are based on timing specifications for the ispLSI 2032VL-180L.
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相關代理商/技術參數(shù) |
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|---|---|
| 2032W-BOX | 制造商:Cooper Wiring Devices 功能描述: |
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| 2032-X0023HX-25B | 制造商:ALLEN-BRADLEY 制造商全稱:Allen-Bradley 功能描述:ElectroGuard |
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